ADIN1110BCPZ-R7 datasheet(86/104 Pages) AD

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Data Sheet

ADIN1110

REGISTERS

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Rev. 0 | 86 of 104

Table 162. Bit Descriptions for AN_STATUS_EXTRA

Bits

Bit Name

Description

Reset

Access

AN_LP_NP_RX

Next Page Request Received from Link Partner.

0x0

R LH

AN_INC_LINK

Incompatible Link Indication. This corresponds to the incompatible link state of IEEE

Standard 802.3 Subclause 98.5.1. Its value is set by the priority resolution function run on

entering the autonegotiation good check state.

0x0

[8:7]

AN_TX_LVL_RSLTN

Autonegotiation Tx Level Result. Transmit level high/low resolution result, determined as

per IEEE Standard 802.3cg Subclause 146.6.4. This is encoded as follows:

0x0

0: not run.

2: success, low transmit levels (1.0 V p-p) selected.

3: success, high transmit levels (2.4 V p-p) selected.

[6:5]

AN_MS_CONFIG_RSLTN

Master/Slave Resolution Result. Determined as per master/slave configuration of IEEE

Standard 802.3. This is encoded as follows:

0x0

0: not run.

1: configuration fault.

2: success, PHY is configured as slave.

3: success, PHY is configured as master.

[4:1]

AN_HCD_TECH

Highest Common Denominator (HCD) PHY Technology. As selected by the priority

resolution function of IEEE Standard 802.3 Subclause 98.2.4.2. Consider all values that

are not shown to be reserved.

0x0

0: null (not run).

1: 10BASE-T1L.

AN_LINK_GOOD

Autonegotiation Complete Indication. This corresponds to the an_link_good state of IEEE

Standard 802.3 Subclause 98.5.1. This signal indicates completion of the autonegotiation

transmission, and that the enabled PHY technology is either bringing up its link or that it

has brought up its link. See also AN_COMPLETE, which is similar, but also indicates that

the PHY link is up.

0x0

PHY Instantaneous Status Register

Device Address: 0x07; Register Address: 0x8030, Reset: 0x0010, Name: AN_PHY_INST_STATUS

This register address provides access to instantaneous status indications. These values are not latched, and the set of indications returned

here are a consistent set, that is, a set of values in effect at the time the register address is read.

Table 163. Bit Descriptions for AN_PHY_INST_STATUS

Bits

Bit Name

Description

Reset

Access

[15:5]

RESERVED

Reserved.

0x0

IS_AN_TX_EN

Autonegotiation Tx Enable Status. Autonegotiation transmit enable. This bit indicates that the

autonegotiation is active and controlling the transmitter, and arbitration has not yet reached the

autonegotiation (AN) good check state or the AN good state. That is, the link_control signals have not been

set to enable.

0x1

IS_CFG_MST

Master Status. If link_control = enable (for example, B10L_LINK_CTRL_EN = 1), this indicates whether the

PHY is operating as master (and not slave).

0x0

IS_CFG_SLV

Slave Status. If link_control = enable (for example, B10L_LINK_CTRL_EN = 1), this indicates whether the

PHY is operating as slave (and not master).

0x0

IS_TX_LVL_HI

Tx Level High Status. Indicates that the PHY is operating with high transmit levels (2.4 V), and not low

transmit levels (1.0 V).

0x0

IS_TX_LVL_LO

Tx Level Low Status. Indicates that the PHY is operating with low transmit levels (1.0 V), and not low

transmit levels (2.4 V).

0x0

Vendor Specific MMD 1 Device Identifier High Register

Device Address: 0x1E; Register Address: 0x0002, Reset: 0x0283, Name: MMD1_DEV_ID1

ADIN1110BCPZ-R7 数据表(PDF) 86 Page - Analog Devices

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