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ADIN1110BCPZ-R7 数据表(PDF) 71 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 71 Page - Analog Devices |
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71 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 71 of 104 Table 118. PHY Clause 45 Register Summary Device Address Register Address Name Description Reset Access 0x1F 0x8028 FG_NFRM_L Frame Generator Number of Frames Low Register. 0x0100 R/W 0x1F 0x8029 FG_DONE Frame Generator Done Register. 0x0000 R 0x1F 0x8055 MAC_IF_LOOPBACK MAC Interface Loopbacks Configuration Register. 0x000A R/W 0x1F 0x805A MAC_IF_SOP_CNTRL MAC Start Of Packet (SOP) Generation Control Register. 0x001B R/W PMA/PMD Control 1 Register Device Address: 0x01; Register Address: 0x0000, Reset: 0x0000, Name: PMA_PMD_CNTRL1 This address corresponds to the PMA/PMD Control Register 1 specified in Clause 45.2.1.1 of Standard 802.3. Note that the reset value of this register is dependent on the hardware configuration pin settings. Table 119. Bit Descriptions for PMA_PMD_CNTRL1 Bits Bit Name Description Reset Access 15 PMA_SFT_RST PMA Software Reset. The PMA software reset bit allows the chip to be reset. When this bit is set, the chip fully initializes, almost equivalent to a hardware reset. This bit is self clearing and returns a value of 1 when a reset is in progress. Otherwise, it returns a value of 0. 0x0 R/W SC [14:12] RESERVED Reserved. 0x0 R 11 PMA_SFT_PD PMA Software Power-Down. The PMA software power-down register puts the chip in a lower power mode. In this mode, most of the circuitry is switched off. However, MDIO access to all registers is still possible. The default value for this register is configurable via the SWPD_EN pin, which allows the chip to be held in power-down mode until an appropriate software initialization is performed. 0x0 R/W [10:1] RESERVED Reserved. 0x0 R 0 LB_PMA_LOC_EN Enables PMA Local Loopback. When this bit is set to 1, the PMA accepts data on the transmit path and returns it on the receive path. When this bit is set to 0, the PMA works in normal mode. 0x0 R/W PMA/PMD Status 1 Register Device Address: 0x01; Register Address: 0x0001, Reset: 0x0002, Name: PMA_PMD_STAT1 This address corresponds to the PMA/PMD Status Register 1 specified in Clause 45.2.1.2 of Standard 802.3. Table 120. Bit Descriptions for PMA_PMD_STAT1 Bits Bit Name Description Reset Access [15:3] RESERVED Reserved. 0x0 R 2 PMA_LINK_STAT_OK_LL PMA Link Status. When read as 1, this bit indicates that the link is up. When read as 0, it indicates that the link has dropped since the last time the bit was read. 0x0 R LL 1 PMA_SFT_PD_ABLE PMA Software Power-Down Able. Indicates that the PMA supports software power-down. 0x1 R 0 RESERVED Reserved. 0x0 R PMA/PMD MMD Devices in Package 1 Register Device Address: 0x01; Register Address: 0x0005, Reset: 0x008B, Name: PMA_PMD_DEVS_IN_PKG1 Table 121. Bit Descriptions for PMA_PMD_DEVS_IN_PKG1 Bits Bit Name Description Reset Access [15:0] PMA_PMD_DEVS_IN_PKG1 PMA/PMD MMD Devices in Package. Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. 0x8B R |
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