ADIN1110BCPZ-R7 datasheet(18/104 Pages) AD

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Data Sheet

ADIN1110

BRINGING UP 10BASE-T1L LINKS

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Rev. 0 | 18 of 104

UNMANAGED PHY OPERATION

For an unmanaged PHY application or lightly managed PHY appli-

cation where there is no software management of the PHY, the

hardware configuration pins determine the operating mode. The

TX2P4_EN pin configures the PHY to advertise the support of both

1.0 V p-p and 2.4 V p-p transmit level operation or to only advertise

support of 1.0 V p-p transmit level operation. The MS_SEL pin

is used to configure the PHY to advertise prefer slave or prefer

master. The SWPD_EN pin must be pulled up at power-up and

reset so that the PHY does not enter software power-down mode

when it exits reset. Once the PHY exits reset, the ADIN1110 starts

autonegotiation and attempts to bring up a link after autonegotiation

completes.

A lightly managed PHY can use the hardware configuration pins to

determine the operation of the PHY and to bring up a 10BASE-T1L

link. Afterwards, software can monitor the operation of the PHY.

MANAGED PHY OPERATION

In a managed PHY application, software is used to configure the

PHY operation using the management interface. The hardware

configuration pins can be used to set the default values of the

registers used to control the transmit amplitude and master/slave

setting. The SWPD_EN pin must be pulled low at power-up and

reset so that the PHY enters software power-down mode when

it exits reset. The PHY remains in software power-down mode

until the software configures the PHY and takes it out of software

power-down mode to start autonegotiation and attempt to bring up

a link.

Power-Up and Reset Complete

To confirm that the MAC has exited reset, read the PHY identifica-

tion register (PHYID). If the reset value of the register (0x283BC91)

can be read, the device has exited reset and is ready for configura-

tion.

Next, the host must read the STATUS0 register and confirm that

the RESETC field is 1. Note that if the RESETC field is 0, and the

SYNC field of the CONFIG0 register is 1, the MAC-PHY is already

configured by the host and, therefore, has not been reset. This

can indicate that the host is reset, but the MAC-PHY has not been

reset.

Write 1 to the RESETC field in the STATUS0 register to clear this

field, and the interrupt pin asserts high.

The PHYINT field of the STATUS0 register also asserts. To

clear this field, the corresponding status registers, PHY_SUB-

SYS_IRQ_STATUS and CRSM_IRQ_STATUS, must be cleared or

masked.

The system ready bit (CRSM_SYS_RDY) can also be read to verify

that the start-up sequence is complete and the system is ready for

normal operation.

The software power-down status bit (CRSM_SFT_PD_RDY) can be

read to check if the device is in the software power-down state. This

bit is configured by the SWPD_EN hardware configuration pin.

MAC Initialization

After power-up or reset, configure the ADIN1110 MAC. Write the

IMASK0 and IMASK1 registers to enable interrupts as required.

Write CONFIG0 and CONFIG2 to set up the required functionality

of the MAC. For example, set the OPEN Alliance chunk size or

enable cut through, if required.

When the MAC is configured, write 1 to the SYNC field in the CON-

FIG0 register to indicate that the MAC configuration is complete.

Configuring the Device for Linking

After power-up or reset, configure the ADIN1110 PHY for the

desired operation for linking. The ADIN1110 may already be config-

ured as required for linking by the hardware configuration pins, but

greater control is available using the management registers.

The autonegotiation process is used to match the operating mode

between a local and remote PHY. For example, autonegotiation is

used to ensure that the modes agree between the two devices on

which PHY operates as master and which as slave. Autonegotiation

is also used to match the transmit level between the two PHYs.

Autonegotiation is enabled by default for the ADIN1110, and it is

strongly recommended to always keep autonegotiation enabled.

Autonegotiation is defined by the IEEE standard and includes a

number of mechanisms to ensure robust linking operation between

PHYs and is the fastest way to bring up a link.

Advertisement of Transmit Level Operating

Mode

The ADIN1110 can support transmit level operation at either 1.0 V

p-p or 2.4 V p-p if the 10BASE-T1L high voltage transmit ability

read only register bit (B10L_TX_LVL_HI_ABLE) is 1 and there is

a 3.3 V supply provided on the AVDD_H pins. The higher transmit

level can support longer reach but also has higher power consump-

tion. The ADIN1110 can support 1.0 V p-p transmit level operation

with a 1.8 V supply on the AVDD_H pins at very low power

consumption. The 1.0 V p-p transmit level operation is required for

intrinsically safe operation.

The ADIN1110 can either be configured to advertise support

of both 1.0 V p-p and 2.4 V p-p transmit level operation

(if B10L_TX_LVL_HI_ABLE = 1) or to advertise support of

only 1.0 V p-p transmit level operation. This is set using

the 10BASE-T1L high level transmit operating mode ability

bit within the BASE-T1 autonegotiation advertisement register

(AN_ADV_B10L_TX_LVL_HI_ABL). 0 = support 1.0 V p-p transmit

level only, and 1 = support both 1.0 V p-p and 2.4 V p-p transmit

level.

ADIN1110BCPZ-R7 数据表(PDF) 18 Page - Analog Devices

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