ADIN1110BCPZ-R7 datasheet(66/104 Pages) AD

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Data Sheet

ADIN1110

REGISTERS

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Rev. 0 | 66 of 104

Table 112. Bit Descriptions for MI_CONTROL

Bits

Bit Name

Description

Reset

Access

MI_SPEED_SEL_LSB

MII Speed Selection LSB. See MI_SPEED_SEL_MSB.

0x0

MI_AN_EN

Autonegotiation Enable. Use the AN_FRC_MODE_EN register to enable forced link configuration

mode. Mirrors AN_EN.

0x1

1 = enable autonegotiation.

0 = disable autonegotiation.

MI_SFT_PD

Software Power-Down. The software power-down register allows the PHY to be placed in software

power-down mode. In this mode, most of the PHY circuitry is switched off. However, MDIO access

to all registers is still possible. The default value for this register is configurable via a pin. This

allows the PHY to be held in reset until an appropriate software initialization is performed. Mirrors

CRSM_SFT_PD.

Pin Dependent

R/W

MI_ISOLATE

MII Isolate. The isolate bit allows the PHY to be isolated from the MII.

0x0

R/W

RESERVED

Reserved.

0x0

R/W SC

MI_FULL_DUPLEX

MII Full Duplex. The duplex mode register cannot be written and always reads as 1 because the

PHY is only able to operate in full duplex mode.

0x1

MI_COLTEST

MII Collision Test. The collision test register cannot be written and always reads as 0 because the

PHY is only able to operate in full duplex mode and does not have a COL pin.

0x0

MI_SPEED_SEL_MSB

MII Speed Selection MSB. The speed selection MSB/LSB registers cannot be written and always

read as 00 because the PHY is only able to operate in 10 Mbps.

0x0

MI_UNIDIR_EN

MII Unidirectional Enable. The unidirectional enable register cannot be written and always reads as

0 because the PHY does not have the ability to transmit data from the MII, regardless of whether or

not it has determined that a valid link is established.

0x0

[4:0]

RESERVED

Reserved.

0x0

MII Status Register

Address: 0x1, Reset: 0x1009, Name: MI_STATUS

This address corresponds to the MII status register specified in Clause 22.2.4.2 of Standard 802.3.

Table 113. Bit Descriptions for MI_STATUS

Bits

Bit Name

Description

Reset

Access

MI_T4_SPRT

100BASE-T4 Ability. The 100BASE-T4 ability bit always reads as 0 to indicate that the PHY does

not support this technology.

0x0

MI_FD100_SPRT

Full Duplex 100BASE-X Ability. The 100BASE-X full duplex ability bit always reads as 0 to indicate

that the PHY does not support this technology.

0x0

MI_HD100_SPRT

Half-Duplex 100BASE-X Ability. The 100BASE-X half-duplex ability bit always reads as 0 to indicate

that the PHY does not support this technology.

0x0

MI_FD10_SPRT

Full Duplex 10 Mbps Ability. The 10 Mbps full duplex ability bit indicates that the PHY supports this

technology.

0x1

MI_HD10_SPRT

Half-Duplex 10 Mbps Ability. The 10 Mbps half-duplex ability bit always reads as 0 to indicate that

the PHY does not support this technology.

0x0

MI_FD_T2_SPRT

Full Duplex 100BASE-T2 Ability. The 100BASE-T2 full duplex ability bits always reads as 0 to

indicate that the PHY does not support this technology.

0x0

MI_HD_T2_SPRT

Half-Duplex 100BASE-T2- Ability. The 100BASE-T2 half-duplex ability bit always reads as 0 to

indicate that the PHY does not support this technology.

0x0

MI_EXT_STAT_SPRT

Extended Status Support. The extended status support bit always reads as 0 to indicate that the

PHY does not provide extended status information in Register 0xF.

0x0

MI_UNIDIR_ABLE

Unidirectional Ability. The unidirectional ability register always reads as 0 to indicate that the PHY

can only transmit data from the MII when it has determined that a valid link is established.

0x0

MI_MF_PREAM_SUP_ABLE

Management Preamble Suppression Ability. The management frame preamble suppression ability

bit always reads as 0 to indicate that the PHY is not able to receive management frames that are

not preceded by the preamble pattern.

0x0

ADIN1110BCPZ-R7 数据表(PDF) 66 Page - Analog Devices

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