 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADIN1110BCPZ-R7 数据表(PDF) 88 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADIN1110BCPZ-R7 数据表(HTML) 88 Page - Analog Devices |
|
|
88 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 88 of 104 System Interrupt Status Register Device Address: 0x1E; Register Address: 0x0010, Reset: 0x1000, Name: CRSM_IRQ_STATUS This address can be used to check which interrupt requests have triggered since the last time it was read. Each bit goes high when the associated event occurs and then latches high until it is unlatched by reading. The bits of CRSM_IRQ_STATUS go high even when the associated interrupts are not enabled. A reserved interrupt being triggered indicates a fatal error in the system. Table 169. Bit Descriptions for CRSM_IRQ_STATUS Bits Bit Name Description Reset Access 15 CRSM_SW_IRQ_LH Software Requested Interrupt Event. 0x0 R LH [14:13] RESERVED Reserved. 0x0 R 12 CRSM_HRD_RST_IRQ_LH Hardware Reset Interrupt. 0x1 R LH [11:0] RESERVED Reserved. 0x0 R LH System Interrupt Mask Register Device Address: 0x1E; Register Address: 0x0020, Reset: 0x1FFE, Name: CRSM_IRQ_MASK Controls whether or not the interrupt signal is asserted in response to various events. Table 170. Bit Descriptions for CRSM_IRQ_MASK Bits Bit Name Description Reset Access 15 CRSM_SW_IRQ_REQ Software Interrupt Request. Software can set this bit to generate an interrupt for system level testing. This bit always reads as 0 as it is self clearing. 0x0 R/W SC [14:13] RESERVED Reserved. 0x0 R 12 CRSM_HRD_RST_IRQ_EN Enable Hardware Reset Interrupt. Note that writing a 0 to this register does not mask the interrupt since this register is initialized when a hardware reset occurs. 0x1 R/W [11:0] RESERVED Reserved. 0xFFE R/W Software Reset Register Device Address: 0x1E; Register Address: 0x8810, Reset: 0x0000, Name: CRSM_SFT_RST Table 171. Bit Descriptions for CRSM_SFT_RST Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_SFT_RST Software Reset Register. The software reset bit allows the chip to be reset. When this bit is set, the chip fully initializes, almost equivalent to a hardware reset. 0x0 R/W SC Software Power-Down Control Register Device Address: 0x1E; Register Address: 0x8812, Reset: 0x0000, Name: CRSM_SFT_PD_CNTRL Table 172. Bit Descriptions for CRSM_SFT_PD_CNTRL Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_SFT_PD Software Power-Down. The software power-down register puts the chip in a lower power mode. In this mode, most of the circuitry is switched off. However, MDIO access to all registers is still possible. The default value for this register is configurable via the SWPD_EN pin, which allows the chip to be held in power-down mode until an appropriate software initialization is performed. Pin dependent R/W |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
