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ADIN1110BCPZ-R7 数据表(PDF) 89 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 89 Page - Analog Devices |
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89 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 89 of 104 PHY Subsystem Reset Register Device Address: 0x1E; Register Address: 0x8814, Reset: 0x0000, Name: CRSM_PHY_SUBSYS_RST Table 173. Bit Descriptions for CRSM_PHY_SUBSYS_RST Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_PHY_SUBSYS_RST PHY Subsystem Reset. The PHY subsystem reset register allows a managed subsystem reset to be initiated. When the PHY subsystem is reset, normal operation resumes, and the bit is self cleared. 0x0 R/W SC PHY MAC Interface Reset Register Device Address: 0x1E; Register Address: 0x8815, Reset: 0x0000, Name: CRSM_MAC_IF_RST Table 174. Bit Descriptions for CRSM_MAC_IF_RST Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_MAC_IF_RST PHY MAC Interface Reset. The PHY MAC interface reset register allows a managed PHY MAC interface reset to be initiated. When the PHY MAC interface is reset, normal operation resumes, and the bit is self cleared. 0x0 R/W SC System Status Register Device Address: 0x1E; Register Address: 0x8818, Reset: 0x0000, Name: CRSM_STAT Table 175. Bit Descriptions for CRSM_STAT Bits Bit Name Description Reset Access [15:2] RESERVED Reserved. 0x0 R 1 CRSM_SFT_PD_RDY Software Power-Down Status. This bit indicates that the system is in the software power-down state. 0x0 R 0 CRSM_SYS_RDY System Ready. This bit indicates that the start-up sequence is complete and the system is ready for normal operation. 0x0 R CRSM Power Management Control Register Device Address: 0x1E; Register Address: 0x8819, Reset: 0x0000, Name: CRSM_PMG_CNTRL Table 176. Bit Descriptions for CRSM_PMG_CNTRL Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_FRC_OSC_EN Force Digital Boot Oscillator Clock Enable. 0x0 R/W CRSM Diagnostics Clock Control Register Device Address: 0x1E; Register Address: 0x882C, Reset: 0x0002, Name: CRSM_DIAG_CLK_CTRL CRSM diagnostics clock control. Table 177. Bit Descriptions for CRSM_DIAG_CLK_CTRL Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x1 R 0 CRSM_DIAG_CLK_EN Enable the Diagnostics Clock. 0x0 R/W |
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