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SH7041A 数据表(PDF) 151 Page - Renesas Technology Corp |
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SH7041A 数据表(HTML) 151 Page - Renesas Technology Corp |
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151 / 923 page  113 No Yes NMI? No Yes User break? No Yes Level 15 interrupt? No Yes I3 to I0 ≤ level 14? No Yes Level 14 interrupt? No Yes Yes I3 to I0 ≤ level 13? No Yes Level 1 interrupt? No Yes I3 to I0 = level 0? No Program execution state IRQOUT = low level*1 Save SR to stack Save PC to stack IRQOUT = high level*2 Branches to exception service routine I3 to I0: Interrupt mask bits of status register Interrupt? Copy accept-interrupt level to I3 to I0 Reads exception vector table Notes: *1 *2 IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1). Thus, it is output when there is a higher priority interrupt request than the one in the I3 to I0 bits of the SR. When the accepted interrupt is sensed by edge, the IRQOUT pin becomes high level at the point when the CPU starts interrupt exception processing instead of instruction execution (before SR is saved to the stack). If the interrupt controller has accepted another interrupt with a higher priority and has output an interrupt request to the CPU, the IRQOUT pin will remain low level. Figure 6.3 Interrupt Sequence Flowchart |
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