SH7041A datasheet(175/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

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• Bits 11–10—DTC Mode 1, 0 (MD1, MD0): These bits designate the DTC transfer mode.

Bit 11 (MD1)

Bit 10 (MD0)

Description

Normal mode

Repeat mode

Block transfer mode

Reserved (setting prohibited)

• Bits 9–8—DTC Data Transfer Size 1, 0 (SZ1, SZ0): These bits designate the data size for data

transfers.

Bit 9 (SZ1)

Bit 8 (SZ0)

Description

Byte (8 bits)

Word (16 bits)

Longword (32 bits)

Reserved (setting prohibited)

• Bit 7—DTC Transfer Mode Select (DTS): When in repeat mode or block transfer mode, this

bit designates whether the source side or destination side will be the repeat area or block area.

Bit 7 (DTS)

Description

Destination side is the repeat area or block area

Source side is the repeat area or block area

• Bit 6—DTC Chain Enable (CHNE): This bit designates whether to perform continuous DTC

data transfers with the same activating source. Continued transfer information is read after the

16th byte from the start address of the previous transfer information.

Bit 6 (CHNE)

Description

DTC data transfer end (activation wait state ensues)

DTC data transfer continue (read continue register information, execute

transfer)

SH7041A 数据表(PDF) 175 Page - Renesas Technology Corp