SH7041A datasheet(236/923 Pages) RENESAS

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SH7041A 数据表(PDF) 236 Page - Renesas Technology Corp

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

236 / 923 page

198

Self-Refresh: When both the RMD and RFSH bits of the RTCSR are set to 1, the

CAS signal and

RAS signal are output and the DRAM enters self-refresh mode, as shown in figure 10.16. Do not

access DRAM during self-refreshes, in order to preserve DRAM data. When performing DRAM

accesses, first cancel the self-refresh, then access only after doing individual refreshes for all row

addresses within the time prescribed for the particular DRAM.

For external bus right requests during self-refreshes, to preserve DRAM data at the time of

releasing the bus rights, only

CASx, RAS, and RDWR are output and the bus rights are released to

the external device with the self-refresh maintained. Consequently, do not perform DRAM

accesses from external devices at such a time.

CASx

RAS

TRp

TRr1

TRr2

TRc

Figure 10.16 Self-Refresh Timing

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