SH7041A datasheet(240/923 Pages) RENESAS

部件名	SH7041A

功能描述	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

240 / 923 page

202

BCR2 and the DIW of the DCR occur. When idle cycles already exist between access cycles, only

the number of empty cycles remaining beyond the specified number of idle cycles are inserted.

Figure 10.20 shows an example of idles between cycles. In this example, 1 idle between CSn

space cycles has been specified, so when a CSm space write immediately follows a CSn space

read cycle, 1 idle cycle is inserted.

CSn

CSm

Data

CSn space read

CSm space write

Idle cycle

WRx

Address

Tidle

Figure 10.20 Idle Cycle Insertion Example

IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read

other external spaces, or for this LSI, to do write accesses. In the same manner, IW21 and IW20

specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1

space read, and IW01 and IW00, the number after a CS0 space read.

DIW specifies the number of idle cycles required, after a DRAM space read either to read other

external spaces (CS space), or for this LSI, to do write accesses.

0 to 3 cycles can be specified for CS space, and 0 to 1 cycle for DRAM space.

SH7041A 数据表(PDF) 240 Page - Renesas Technology Corp