MMPF0200Z datasheet(17/118 Pages) NXP

17 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

General Description

Functional Block Diagram

5.2

Functional Block Diagram

Figure 5. Functional Block Diagram

5.3

Functional Description

5.3.1

Power Generation

The PF0200Z PMIC features three buck regulators (up to four independent outputs), one boost regulator, six general purpose

LDOs, one switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral

devices.

The number of independent buck regulator outputs can be configured from three to four, thereby providing flexibility to operate

with higher current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current

demands. The SW3 regulator can be configured as single phase or with two independent outputs. The buck regulators provide

the supply to processor cores and to other low-voltage circuits such as IO and memory. Dynamic voltage scaling is provided to

allow controlled supply rail adjustments for the processor cores and/or other circuitry.

Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the

main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A

specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operating with or

without VTT termination. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on

the i.MX processors; VSNVS may be powered from VIN, or from a coin cell.

Logic and Control

Switching Regulators

SW1A/B

(0.3 to 1.875V, 2.5A)

Linear Regulators

SW2

(0.4 to 3.3V, 1.5A)

SW3A/B

(0.4 to 3.3V)

Configurable 2.5A or

1.25A+1.25A

Boost Regulator

(5 to 5.15V, 600mA)

USB OTG Supply

VGEN1

(0.8 to 1.55V, 100mA)

VGEN2

(0.8 to 1.55V, 250mA)

VGEN3

(1.8 to 3.3V, 100mA)

VGEN4

(1.8 to 3.3V, 350mA)

VGEN5

(1.8 to 3.3V, 100mA)

VGEN6

(1.8 to 3.3V, 200mA)

Bias & References

Parallel MCU Interface

Regulator Control

VSNVS

(1.0 to 3.0V, 400uA)

RTC supply with coin cell

charger

PF0200Z Functional Internal Block Diagram

I2C Communication & Registers

Power Generation

Fault Detection and Protection

DDR Voltage Reference

Current Limit

Short-Circuit

Internal Core Voltage Reference

Thermal

OTP Startup Configuration

Sequence and

timing

OTP Prototyping

(Try before buy)

Voltage

Phasing and

Frequency Selection

MMPF0200Z 数据表(PDF) 17 Page - NXP Semiconductors

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