MMPF0200Z datasheet(18/118 Pages) NXP

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Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

General Description

Functional Description

5.3.2

Control Logic

The PF0200Z PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing

including interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-

up section, or by configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP

configuration.

The PF0200Z PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also

ensures supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A

charger for the coin cell is included as well.

5.3.2.1

Interface Signals

PWRON

PWRON is an input signal to the IC that generates a turn-on event. It can be configured to detect a level, or an edge using the

PWRON_CFG bit. Refer to section Turn On Events for more details.

STANDBY

STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits

standby mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section

Standby Mode for more details.

Note: When operating the PMIC at VIN

 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to

provide VSNVS, or the PMIC will not reliably enter and exit the STANDBY mode.

RESETBMCU

RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted

2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal

can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a

turn-off event.

When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults

occurred during start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The

PF0200Z is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault

persists, the sequence described above will be repeated. To enter the fault mode, set bit OTP_PG_EN of register

OTP PWRGD EN to “1”. This register, 0xE8, is located on Extended Page 1 of the register map. To test the fault mode, the bit

may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses.

SDWNB

SDWNB is an open-drain, active low output that notifies the processor of an imminent PMIC shutdown. It is asserted low for one

32 kHz clock cycle before powering down and is then de-asserted in the OFF state.

INTB

INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB

is de-asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.

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