MMPF0200Z datasheet(88/118 Pages) NXP

88 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Control Interface I2C Block Description

Coin Cell Specifications

6.5

Control Interface I2C Block Description

The PF0200Z contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these

registers the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.

The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections

in the SCL and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than

20 ns. This can be accomplished by reducing the drive strength of the I2C master via software. The i.MX6 I2C driver defaults to

a 40 ohm drive strength. It is recommended to use a drive strength of 80 ohm or higher to increase the edge times. Alternatively,

this can be accomplished by using small capacitors from SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL

and SDA to ground for bus pull-up resistors of 4.8 kohm.

6.5.1

I2C Device ID

I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for

bus conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to One Time

Programmability (OTP) for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general

call addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the

new slave address; these bits take affect right away.

6.5.2

I2C Operation

The I2C mode of the interface is implemented generally following the Fast mode definition which supports up to 400 kbits/s

operation (exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) Timing

diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at:

http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf

I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and

each byte will be sent out unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication.

The host sends a master command packet after driving the start condition. The device will respond to the host if the master

command packet contains the corresponding slave address. In the following examples, the device is shown always responding

with an ACK to transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction

and retry the transaction.

Figure 22. I2C Write Example

Table 99. Coin Cell Charger Specifications

Parameter

Typ

Unit

Voltage Accuracy

100

Coin Cell Charge Current in On mode ICOINHI

A

Current Accuracy

Device

Address

Packet

Type

START

R / W

Host SDA

Slave SDA

Master Driven Data

( byte

0 )

STOP

Host can

also drive

another

Start instead

of Stop

MMPF0200Z 数据表(PDF) 88 Page - NXP Semiconductors

MMPF0200Z 数据表(HTML) 88 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载