MMPF0200Z datasheet(32/118 Pages) NXP

32 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Power Generation

The sense bit will show the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical

switch debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e.,

unintentional) key press. The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms

interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with

PWRONDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode.

6.4.2.2

Turn Off Events

PWRON Pin

The PWRON pin is used to power off the PF0200Z. The PWRON pin can be configured with OTP to power off the PMIC under

the following two conditions:

1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.

2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0

seconds. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

Thermal Protection

If the die temperature surpasses a given threshold, the thermal protection circuit will power off the PMIC to avoid damage. A turn-

on event will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature

decreases below a given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power

Dissipation section for more detailed information.

Undervoltage Detection

When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine will transition to the Coin Cell

mode.

6.4.3

Power Tree

The PF0200Z PMIC features four buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination,

and a DDR voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as

well as the boost regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be

tied to VIN, whether they are powered on or off. The six general use LDO regulators are directly supplied from the main input

supply or from the switching regulators depending on the application requirements. Since VREFDDR is intended to provide DDR

memory reference voltage, it should be supplied by any rail supplying voltage to DDR memories; the typical application

recommends the use of SW3 as the input supply for VREFDDR. VSNVS is supplied by either the main input supply or the coin

cell. Refer to Table 26 for a summary of all power supplies provided by the PF0200Z.

Table 25. PWRON Hardware Debounce Bit Settings

Bits

State

Turn On

Debounce (ms)

Falling Edge INT

Debounce (ms)

Rising Edge INT

Debounce (ms)

PWRONDBNC[1:0]

0.0

31.25

125

31.25

750

31.25

Notes

35.

The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.

MMPF0200Z 数据表(PDF) 32 Page - NXP Semiconductors

MMPF0200Z 数据表(HTML) 32 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

MMPF0200Z 数据表(PDF) 32 Page - NXP Semiconductors

MMPF0200Z 数据表(HTML) 32 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载