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MMPF0200Z 数据表(PDF) 38 Page - NXP Semiconductors

部件名 MMPF0200Z
功能描述  12 Channel Configurable Power Management Integrated Circuit
PDF  118 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MMPF0200Z 数据表(HTML) 38 Page - NXP Semiconductors

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Analog Integrated Circuit Device Data
38
Freescale Semiconductor
PF0200Z
Functional Block Requirements and Behaviors
Power Generation
Figure 10. Voltage Stepping with DVS
Regulator Phase Clock
The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 34. By default, each regulator is initialized at
90 ° out of phase with respect to each other. For example, SW1A/B is set to 0 °, SW2 is set to 90 ° and SW3A/B is set to 180 °
by default at power up.
The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 36 shows
the selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at
different frequencies to have different relative switching phases. However, not all combinations are practical. For example,
2.0 MHz, 90 ° and 4.0 MHz, 180 ° are the same in terms of phasing. Table 35 shows the optimum phasing when using more than
one switching frequency.
Table 34. Regulator Phase Clock Selection
SWxPHASE[1:0]
Phase of Clock Sent to Regulator
(degrees)
00
0
01
90
10
180
11
270
Table 35. Optimum Phasing
Frequencies
Optimum Phasing
1.0 MHz
2.0 MHz
0 °
180 °
1.0 MHz
4.0 MHz
0 °
180 °
2.0 MHz
4.0 MHz
0 °
180 °
1.0 MHz
2.0 MHz
4.0 MHz
0 °
90 °
90 °
Actual
Output Voltage
Example
Actual Output
Voltage
Possible
Output Voltage
Window
Internally
Controlled Steps
Output Voltage
with light Load
Initial
Set Point
Voltage
Change
Request
Internally
Controlled Steps
Output
Voltage
Requested
Set Point
Initiated by I2C Programming, Standby Control
Request for
Higher Voltage
Request for
Lower Voltage



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