MMPF0200Z datasheet(63/118 Pages) NXP

63 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Power Generation

6.4.5

Boost Regulator

SWBST is a boost regulator with a programmable output from 5.0 to 5.15 V. SWBST can supply the VUSB regulator for the USB

PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator will cause the

SWBSTOUT and SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching

NMOS transistor is integrated on-chip. Figure 18 shows the block diagram and component connection for the boost regulator.

Figure 18. Boost Regulator Architecture

6.4.5.1

SWBST Setup and Control

Boost regulator control is done through a single register SWBSTCTL described in Table 72. SWBST is included in the power-up

sequence if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.

Table 72. Register SWBSTCTL - ADDR 0x66

Name

Bit #

R/W

Default

Description

SWBST1VOLT

1:0

R/W

0x00

Set the output voltage for SWBST

00 = 5.000 V

01 = 5.050 V

10 = 5.100 V

11 = 5.150 V

SWBST1MODE

3:2

0x02

Set the Switching mode on Normal operation

00 = OFF

01 = PFM

10 = Auto (Default)(47)

11 = APS

UNUSED

–

0x00

UNUSED

SWBST1STBYMODE

6:5

R/W

0x02

Set the Switching mode on Standby

00 = OFF

01 = PFM

10 = Auto (Default)(47)

11 = APS

SWBSTLX

VOBST

Driver

Controller

Internal

Compensation

I2C

Interface

SWBSTMODE

VREFUV

VREF

VIN

LBST

CINBST

DBST

SWBSTFB

RSENSE

VREFSC

SWBSTFAULT

COSWBST

SWBSTIN

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