MMPF0200Z datasheet(53/118 Pages) NXP

53 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Power Generation

6.4.4.5

SW3A/B

SW3A/B are 1.25 to 2.5 A rated buck regulators, depending on the configuration. Table 28 describes the available switching

modes and Table 29 show the actual configuration options for the SW3xMODE[3:0] bits.

SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following

configurations are available:

• A single phase

• Independent regulators

The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 57 shows the options for the

SW3CFG[1:0] bits.

SW3A/B Single Phase

In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 15. This

configuration reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left

open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.

Figure 15. SW3A/B Single Phase Block Diagram

Table 57. SW3 Configuration

SW3_CONFIG[1:0]

Description

A/B Single Phase

Reserved

A/B Independent

Driver

Controller

SW3AIN

SW3ALX

SW3AFB

ISENSE

COSW3A

CINSW3A

LSW3A

I2C

Interface

SW3

SW3AMODE

SW3AFAULT

VIN

Driver

Controller

SW3BIN

SW3BLX

ISENSE

CINSW3B

SW3BMODE

SW3BFAULT

VIN

Internal

Compensation

VREF

DAC

I2C

Internal

Compensation

VREF

DAC

I2C

SW3BFB

MMPF0200Z 数据表(PDF) 53 Page - NXP Semiconductors

MMPF0200Z 数据表(HTML) 53 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载