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MMPF0200Z 数据表(PDF) 96 Page - NXP Semiconductors

部件名 MMPF0200Z
功能描述  12 Channel Configurable Power Management Integrated Circuit
PDF  118 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MMPF0200Z 数据表(HTML) 96 Page - NXP Semiconductors

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Analog Integrated Circuit Device Data
96
Freescale Semiconductor
PF0200Z
Functional Block Requirements and Behaviors
Control Interface I2C Block Description
Reset: Reset signals are color coded based on the following legend.
Default: The value after reset, as noted in the Default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read / Write bits that are initialized at start-up, based on the OTP fuse settings or default if
VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits that
may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog
block, for instance the sense bits for the interrupts.
6.5.6.1
Register map
Bits reset by SC and VCOREDIG_PORB
Bits reset by PWRON or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
Table 120. Functional Page
BITS[7:0]
Add
Register
Name
R/W
Default
7
6
5
4
3
2
1
0
00
DeviceID
R
8'b0001_0001
–
–
–
–
DEVICE ID [3:0]
00
0
1
0
0
0
1
03
SILICONREVID
R
8'b0001_0000
FULL_LAYER_REV[3:0]
METAL_LAYER_REV[3:0]
XX
X
X
X
X
X
X
04
FABID
R
8'b0000_0000
–
–
–
–
FAB[1:0]
FIN[1:0]
00
0
0
0
0
0
0
05
INTSTAT0
RW1C 8'b0000_0000
––
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
PWRONI
00
0
0
0
0
0
0
06
INTMASK0
R/W
8'b0011_1111
––
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
PWRONM
00
1
1
1
1
1
1
07
INTSENSE0
R
8'b00xx_xxxx
VDDOTPS
RSVD
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
PWRONS
00
x
x
x
x
x
x
08
INTSTAT1
RW1C 8'b0000_0000
–
RSVD
SW3BFAULTI
SW3AFAULTI
SW2FAULTI
RSVD
SW1BFAULTI
SW1AFAULTI
00
0
0
0
0
0
0
09
INTMASK1
R/W
8'b0111_1111
–
RSVD
SW3BFAULTM SW3AFAULTM SW2FAULTM
RSVD
SW1BFAULTM
SW1AFAULTM
01
1
1
1
1
1
1
0A
INTSENSE1
R
8'b0xxx_xxxx
–
RSVD
SW3BFAULTS SW3AFAULTS
SW2FAULTS
RSVD
SW1BFAULTS
SW1AFAULTS
0x
x
x
x
x
x
x
0E
INTSTAT3
RW1C 8'b0000_0000
OTP_ECCI
–
–
–
–
–
–
SWBSTFAULTI
00
0
0
0
0
0
0



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