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MMPF0200Z 数据表(PDF) 36 Page - NXP Semiconductors |
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MMPF0200Z 数据表(HTML) 36 Page - NXP Semiconductors |
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36 / 118 page  Analog Integrated Circuit Device Data 36 Freescale Semiconductor PF0200Z Functional Block Requirements and Behaviors Power Generation Table 29 summarizes the Buck regulator programmability for Normal and Standby modes. Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate of the output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic Voltage Scaling. The output voltage options are the same for Normal and Standby modes for each regulator. When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage programmed in its voltage register. Any regulators whose SWxOMODE bit is set to “1” will enter Sleep mode if a PWRON turn-off event occurs, and any regulator whose SWxOMODE bit is set to “0” will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state. Any regulator whose SWxOMODE bit is set to “0” will be powered up with the same delay in the start-up sequence as when powering On from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings. Table 23 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B. Dynamic Voltage Scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. 1. Normal operation: The output voltage is selected by I2C bits SW1AB[5:0] for SW1A/B and SWx[6:0] for SW2 and SW3A/B. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 32 and Table 33. 2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SW1ABSTBY[5:0] for SW1A/B and by bits SWxSTBY[6:0] for SW2 and SW3A/B. Voltage transitions initiated by a Standby event are governed by the SW1ABDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively. Table 29. Regulator Mode Control SWxMODE[3:0] Normal Mode Standby Mode 0000 Off Off 0001 PWM Off 0010 Reserved Reserved 0011 PFM Off 0100 APS Off 0101 PWM PWM 0110 PWM APS 0111 Reserved Reserved 1000 APS APS 1001 Reserved Reserved 1010 Reserved Reserved 1011 Reserved Reserved 1100 APS PFM 1101 PWM PFM 1110 Reserved Reserved 1111 Reserved Reserved |
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