MCP2518FD datasheet(30/96 Pages) MICROCHIP

30 / 96 page

MCP2518FD

DS20006027A-page 30

 2019 Microchip Technology Inc.

CiTDC – TRANSMITTER DELAY COMPENSATION REGISTER

U-0

R/W-0

—

EDGFLTEN

SID11EN

bit 31

bit 24

U-0

R/W-1

R/W-0

—

TDCMOD<1:0>

bit 23

bit 16

U-0

R/W-0

R/W-1

R/W-0

—

TDCO<6:0>

bit 15

bit 8

U-0

R/W-0

—

TDCV<5:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-26

Unimplemented: Read as ‘0’

bit 25

EDGFLTEN: Enable Edge Filtering during Bus Integration state bit

1 = Edge Filtering enabled, according to ISO 11898-1:2015

0 = Edge Filtering disabled

bit 24

SID11EN: Enable 12-Bit SID in CAN FD Base Format Messages bit

1 = RRS is used as SID11 in CAN FD base format messages: SID<11:0> = {SID<10:0>, SID11}

0 = Don’t use RRS; SID<10:0> according to ISO 11898-1:2015

bit 23-18

Unimplemented: Read as ‘0’

bit 17-16

TDCMOD<1:0>: Transmitter Delay Compensation Mode bits; Secondary Sample Point (SSP)

10-11 = Auto; measure delay and add TDCO.

01 = Manual; Don’t measure, use TDCV + TDCO from register

00 = TDC Disabled

bit 15

Unimplemented: Read as ‘0’

bit 14-8

TDCO<6:0>: Transmitter Delay Compensation Offset bits; Secondary Sample Point (SSP)

Two’s complement; offset can be positive, zero, or negative.

011 1111 = 63 x TSYSCLK

...

000 0000 = 0 x TSYSCLK

...

111 1111 = –64 x TSYSCLK

bit 7-6

Unimplemented: Read as ‘0’

bit 5-0

TDCV<5:0>: Transmitter Delay Compensation Value bits; Secondary Sample Point (SSP)

11 1111 = 63 x TSYSCLK

...

00 0000 = 0 x TSYSCLK

Note 1:

This register can only be modified in Configuration mode.

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