MCP2518FD datasheet(53/96 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006027A-page 53

MCP2518FD

CiFIFOCONm – FIFO CONTROL REGISTER m, (m = 1 TO 31)

R/W-0

PLSIZE<2:0>( 1)

FSIZE<4:0>( 1)

bit 31

bit 24

U-0

R/W-1

R/W-0

—

TXAT<1:0>

TXPRI<4:0>

bit 23

bit 16

U-0

S/HC-1

R/W/HC-0

S/HC-0

—

FRESET( 3)

TXREQ( 2)

UINC

bit 15

bit 8

R/W-0

TXEN( 1)

RTREN

RXTSEN( 1)

TXATIE

RXOVIE

TFERFFIE

TFHRFHIE

TFNRFNIE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-29

PLSIZE<2:0>: Payload Size bits( 1)

000 = 8 data bytes

001 = 12 data bytes

010 = 16 data bytes

011 = 20 data bytes

100 = 24 data bytes

101 = 32 data bytes

110 = 48 data bytes

111 = 64 data bytes

bit 28-24

FSIZE<4:0>: FIFO Size bits( 1)

0_0000 = FIFO is 1 Message deep

0_0001 = FIFO is 2 Messages deep

0_0010 = FIFO is 3 Messages deep

...

1_1111 = FIFO is 32 Messages deep

bit 23

Unimplemented: Read as ‘0’

bit 22-21

TXAT<1:0>: Retransmission Attempts bits

This feature is enabled when CiCON.RTXAT is set.

00 = Disable retransmission attempts

01 = Three retransmission attempts

10 = Unlimited number of retransmission attempts

11 = Unlimited number of retransmission attempts

bit 20-16

TXPRI<4:0>: Message Transmit Priority bits

00000 = Lowest Message Priority

...

11111 = Highest Message Priority

Note 1:

These bits can only be modified in Configuration mode.

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

FRESET is set while in Configuration mode and is automatically cleared in Normal mode.

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