MCP2518FD datasheet(58/96 Pages) MICROCHIP

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MCP2518FD

DS20006027A-page 58

 2019 Microchip Technology Inc.

CiFIFOUAm – FIFO USER ADDRESS REGISTER m, (m = 1 TO 31)

R-x

FIFOUA<31:24>

bit 31

bit 24

R-x

FIFOUA<23:16>

bit 23

bit 16

R-x

FIFOUA<15:8>

bit 15

bit 8

R-x

FIFOUA<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-0

FIFOUA<31:0>: FIFO User Address bits

TXEN = 1 (FIFO is configured as a Transmit FIFO)

A read of this register will return the address where the next message is to be written (FIFO head).

TXEN = 0 (FIFO is configured as a Receive FIFO)

A read of this register will return the address where the next message is to be read (FIFO tail).

Note 1:

This bit is not guaranteed to read correctly in Configuration mode and should only be accessed when the

module is not in Configuration mode.

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