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MCP2518FD 数据表(PDF) 62 Page - Microchip Technology |
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MCP2518FD 数据表(HTML) 62 Page - Microchip Technology |
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62 / 96 page  MCP2518FD DS20006027A-page 62 2019 Microchip Technology Inc. REGISTER 3-34: CiMASKm – MASK REGISTER m, (m = 0 TO 31) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MIDE MSID11 MEID<17:13> bit 31 bit 24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MEID<12:5> bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MEID<4:0> MSID<10:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 Unimplemented: Read as ‘0’ bit 30 MIDE: Identifier Receive mode bit 1 = Match only message types (standard or extended ID) that correspond to EXIDE bit in filter 0 = Match both standard and extended message frames if filters match bit 29 MSID11: Standard Identifier Mask bit bit 28-11 MEID<17:0>: Extended Identifier Mask bits In DeviceNet mode, these are the mask bits for the first 18 data bits bit 10-0 MSID<10:0>: Standard Identifier Mask bits |
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