MCP2518FD datasheet(54/96 Pages) MICROCHIP

54 / 96 page

MCP2518FD

DS20006027A-page 54

 2019 Microchip Technology Inc.

bit 15-11

Unimplemented: Read as ‘0’

bit 10

FRESET: FIFO Reset bit( 3)

1 = FIFO will be reset when bit is set; cleared by hardware when FIFO was reset. User should wait

until this bit is clear before taking any action.

0 = No effect

bit 9

TXREQ: Message Send Request bit( 2)

TXEN = 1 (FIFO configured as a Transmit FIFO)

1 = Requests sending a message; the bit will automatically clear when all the messages queued in

the FIFO are successfully sent.

0 = Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

TXEN = 0 (FIFO configured as a Receive FIFO)

This bit has no effect.

bit 8

UINC: Increment Head/Tail bit

TXEN = 1 (FIFO configured as a Transmit FIFO)

When this bit is set, the FIFO head will increment by a single message.

TXEN = 0 (FIFO configured as a Receive FIFO)

When this bit is set, the FIFO tail will increment by a single message.

bit 7

TXEN: TX/RX FIFO Selection bit( 1)

1 = Transmit FIFO

0 = Receive FIFO

bit 6

RTREN: Auto RTR Enable bit

1 = When a remote transmit is received, TXREQ will be set.

0 = When a remote transmit is received, TXREQ will be unaffected.

bit 5

RXTSEN: Received Message Time Stamp Enable bit( 1)

1 = Capture time stamp in received message object in RAM.

0 = Don’t capture time stamp.

bit 4

TXATIE: Transmit Attempts Exhausted Interrupt Enable bit

1 = Enable interrupt

0 = Disable interrupt

bit 3

RXOVIE: Overflow Interrupt Enable bit

1 = Interrupt enabled for overflow event

0 = Interrupt disabled for overflow event

bit 2

TFERFFIE: Transmit/Receive FIFO Empty/Full Interrupt Enable bit

TXEN = 1 (FIFO configured as a Transmit FIFO)

Transmit FIFO Empty Interrupt Enable

1 = Interrupt enabled for FIFO empty

0 = Interrupt disabled for FIFO empty

TXEN = 0 (FIFO configured as a Receive FIFO)

Receive FIFO Full Interrupt Enable

1 = Interrupt enabled for FIFO full

0 = Interrupt disabled for FIFO full

CiFIFOCONm – FIFO CONTROL REGISTER m, (m = 1 TO 31) (CONTINUED)

Note 1:

These bits can only be modified in Configuration mode.

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

FRESET is set while in Configuration mode and is automatically cleared in Normal mode.

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