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MCP2518FD 数据表(PDF) 56 Page - Microchip Technology |
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MCP2518FD 数据表(HTML) 56 Page - Microchip Technology |
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56 / 96 page ![]() MCP2518FD DS20006027A-page 56 2019 Microchip Technology Inc. REGISTER 3-30: CiFIFOSTAm – FIFO STATUS REGISTER m, (m = 1 TO 31) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 31 bit 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — FIFOCI<4:0>( 1) bit 15 bit 8 HS/C-0 HS/C-0 HS/C-0 HS/C-0 HS/C-0 R-0 R-0 R-0 TXABT( 2)( 3) TXLARB ( 2)( 3) TXERR( 2)( 3) TXATIF RXOVIF TFERFFIF TFHRFHIF TFNRFNIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as ‘0’ bit 12-8 FIFOCI<4:0>: FIFO Message Index bits( 1) TXEN = 1 (FIFO is configured as a Transmit FIFO) A read of this bit field will return an index to the message that the FIFO will next attempt to transmit. TXEN = 0 (FIFO is configured as a Receive FIFO) A read of this bit field will return an index to the message that the FIFO will use to save the next message bit 7 TXABT: Message Aborted Status bit( 2)( 3) 1 = Message was aborted 0 = Message completed successfully bit 6 TXLARB: Message Lost Arbitration Status bit( 2)( 3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 5 TXERR: Error Detected During Transmission bit( 2)( 3) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 4 TXATIF: Transmit Attempts Exhausted Interrupt Pending bit TXEN = 1 (FIFO is configured as a Transmit FIFO) 1 = Interrupt pending 0 = Interrupt not pending TXEN = 0 (FIFO is configured as a Receive FIFO) Read as ‘0’ Note 1: FIFOCI<4:0> gives a zero-indexed value to the message in the FIFO. If the FIFO is 4 messages deep (FSIZE = 5’h03) FIFOCI will take on a value of 0 to 3 depending on the state of the FIFO. 2: This bit is cleared when TXREQ is set or by writing a 0 using the SPI. 3: This bit is updated when a message completes (or aborts) or when the FIFO is reset. |
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