MCP2518FD datasheet(71/96 Pages) MICROCHIP

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DS20000000A-page 71

MCP2518FD

4.3.2

SFR READ WITH CRC – READ_CRC

Figure 4-8 illustrates the READ_CRC instruction,

while accessing SFR. The instruction starts with nCS

going low. The Command (C<3:0> = 0b1011), is

followed by the Address (A<11:0>), and the number of

data bytes (N<7:0>). Afterwards, the data byte from

address A (DB[A]) is shifted out, followed by the data

byte from address A+1 (DB[A+1]). Any number of data

bytes can be read. Next the CRC is shifted out

(CRC<15:0>). The instruction ends when nCS goes

high.

The CRC is provided to the microcontroller. The micro-

controller checks the CRC. No interrupt is generated

on CRC mismatch during a READ_CRC command

inside the MCP2518FD device.

If nCS goes high before the last byte of the CRC is

shifted out, a CRC Form Error interrupt is generated:

CRC.FERRIF.

4.3.3

SFR WRITE

WITH CRC – WRITE_CRC

Figure 4-9 illustrates the WRITE_CRC instruction,

while accessing SFR. The instruction starts with nCS

going low. The Command (C<3:0> = 0b1010), is fol-

lowed by the Address (A<11:0>), and the number of

data bytes (N<7:0>). Afterwards, the data byte is

shifted into address A (DB[A]), next into address A+1

(DB[A+1]). Any number of data bytes can be written.

Next the CRC is shifted in (CRC<15:0>). The instruc-

tion ends when nCS goes high.

The SFR is written to the register after the data byte

was shifted in on SDI, with the falling edge on SCK.

Data bytes are written to the register before the CRC

is checked.

The CRC is checked at the end of the write access. In

case of a CRC mismatch, a CRC Error interrupt is

generated: CRC.CRCERRIF.

If nCS goes high before the last byte of the CRC is

shifted in, a CRC Form Error interrupt is generated:

CRC.FERRIF.

FIGURE 4-8:

SFR READ WITH CRC INSTRUCTION

FIGURE 4-9:

SFR WRITE WITH CRC INSTRUCTION

4.3.4

SFR WRITE SAFE

WITH CRC – WRITE_SAFE

This instruction ensures that only correct data is writ-

ten to the SFR.

Figure 4-10 illustrates the WRITE_SAFE instruction,

while accessing SFR. The instruction starts with nCS

going low. The Command (C<3:0> = 0b1100), is fol-

lowed by the Address (A<11:0>). Afterwards, one data

byte is shifted into address A (DB[A]). Next the CRC

(CRC<15:0>) is shifted in. The instruction ends when

nCS goes high.

The data byte is only written to the SFR after the CRC

is checked and if it matches.

If the CRC mismatches, the data byte is not written to

the SFR and a CRC Error interrupt is generated:

CRC.CRCERRIF.

If nCS goes high before the last byte of the CRC is

shifted in, a CRC Form Error interrupt is generated:

CRC.FERRIF.

FIGURE 4-10:

SFR WRITE SAFE WITH CRC INSTRUCTION

0b1011

A<11:0>

DB[A]

DB[A+1]

DB[A+n-1]

nCS Low

CRC<15:8>

CRC<7:0>

nCS High

N<7:0>

0b1010

A<11:0>

DB[A]

DB[A+1]

DB[A+n-1]

nCS Low

CRC<15:8>

CRC<7:0>

nCS High

N<7:0>

0b1100

A<11:0>

DB[A]

CRC<15:8>

CRC<7:0>

nCS Low

nCS High

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