MCP2518FD datasheet(57/96 Pages) MICROCHIP

57 / 96 page

 2019 Microchip Technology Inc.

DS20006027A-page 57

MCP2518FD

bit 3

RXOVIF: Receive FIFO Overflow Interrupt Flag bit

TXEN = 1 (FIFO is configured as a Transmit FIFO)

Unused, Read as ‘0’

TXEN = 0 (FIFO is configured as a Receive FIFO)

1 = Overflow event has occurred

0 = No overflow event has occurred

bit 2

TFERFFIF: Transmit/Receive FIFO Empty/Full Interrupt Flag bit

TXEN = 1 (FIFO is configured as a Transmit FIFO)

Transmit FIFO Empty Interrupt Flag

1 = FIFO is empty

0 = FIFO is not empty; at least one message queued to be transmitted

TXEN = 0 (FIFO is configured as a Receive FIFO)

Receive FIFO Full Interrupt Flag

1 = FIFO is full

0 = FIFO is not full

bit 1

TFHRFHIF: Transmit/Receive FIFO Half Empty/Half Full Interrupt Flag bit

TXEN = 1 (FIFO is configured as a Transmit FIFO)

Transmit FIFO Half Empty Interrupt Flag

1 = FIFO is ≤ half full

0 = FIFO is > half full

TXEN = 0 (FIFO is configured as a Receive FIFO)

Receive FIFO Half Full Interrupt Flag

1 = FIFO is ≥ half full

0 = FIFO is < half full

bit 0

TFNRFNIF: Transmit/Receive FIFO Not Full/Not Empty Interrupt Flag bit

TXEN = 1 (FIFO is configured as a Transmit FIFO)

Transmit FIFO Not Full Interrupt Flag

1 = FIFO is not full

0 = FIFO is full

TXEN = 0 (FIFO is configured as a Receive FIFO)

Receive FIFO Not Empty Interrupt Flag

1 = FIFO is not empty, contains at least one message

0 = FIFO is empty

CiFIFOSTAm – FIFO STATUS REGISTER m, (m = 1 TO 31) (CONTINUED)

Note 1:

FIFOCI<4:0> gives a zero-indexed value to the message in the FIFO. If the FIFO is 4 messages deep

(FSIZE = 5’h03) FIFOCI will take on a value of 0 to 3 depending on the state of the FIFO.

This bit is cleared when TXREQ is set or by writing a 0 using the SPI.

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

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