R5F104FCAFP datasheet(143/207 Pages) RENESAS

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RL78/G13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0131EJ0350 Rev.3.50

143 of 200

Jun 30, 2020

(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)

(TA = –40 to +105°C, 2.4 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

SCKp cycle time Note 5

tKCY2

4.0 V

≤ EVDD0 ≤ 5.5 V

20 MHz < fMCK

16/fMCK

fMCK

≤ 20 MHz

12/fMCK

2.7 V

≤ EVDD0 ≤ 5.5 V

16 MHz < fMCK

16/fMCK

fMCK

≤ 16 MHz

12/fMCK

2.4 V

≤ EVDD0 ≤ 5.5 V

16/fMCK

12/fMCK and 1000

SCKp high-/low-level

width

tKH2,

tKL2

4.0 V

≤ EVDD0 ≤ 5.5 V

tKCY2/2 – 14

2.7 V

≤ EVDD0 ≤ 5.5 V

tKCY2/2 – 16

2.4 V

≤ EVDD0 ≤ 5.5 V

tKCY2/2 – 36

SIp setup time

(to SCKp

↑) Note 1

tSIK2

2.7 V

≤ EVDD0 ≤ 5.5 V

1/fMCK+40

2.4 V

≤ EVDD0 ≤ 5.5 V

1/fMCK+60

SIp hold time

(from SCKp

↑) Note 2

tKSI2

2.4 V

≤ EVDD0 ≤ 5.5 V

1/fMCK+62

Delay time from SCKp

↓

to SOp output Note 3

tKSO2

C = 30 pF Note 4

2.7 V

≤ EVDD0 ≤ 5.5 V

2/fMCK+66

2.4 V

≤ EVDD0 ≤ 5.5 V

2/fMCK+113

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes

“from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SOp output lines.

5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps

Caution

Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin

by using port input mode register g (PIMg) and port output mode register g (POMg).

Remarks 1.

p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),

n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).

m: Unit number,

n: Channel number (mn = 00 to 03, 10 to 13))

CSI mode connection diagram (during communication at same potential)

RL78

microcontroller

SCKp

SOp

SCK

User device

SIp

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