P9222-R datasheet(45/58 Pages) RENESAS

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P9222-R/RN Datasheet

May 5, 2022

Clearing a single interrupt:

Clearing a single interrupt is a two-step process using the INT_Clear_L (0x3A) and COM (0x4E) registers:

1. In the INT_Clear_L (0x3A) register, set the bit that corresponds to the interrupt that will be cleared.

2. In the COM (0x4E) register, set bit 5 to instruct the processor to clear the interrupt.

Note: Only the interrupt(s) that are selected with the INT_Clear_L (0x3A) register will be cleared.

Table 17. Vout Set Register, Vout_Set (0x3C)

Address

and Bit

R/W

Default

Value

Function and Description

0x3C [7:0]

Vout_Set

R/W

0x32

Set the output voltage of the main LDO in 0.1V units. BPP default value: 0x32.

Example: To set Vout to 5.5V, write 0d55 (0x37).

Table 18. ILIM Set Register, ILIM_Set (0x3D)

Address

and Bit

R/W

Default

Value

Function and Description

0x3D [7:0]

ILIM_Set[7:0]

R/W

0x0F

Main LDO output current limit (by which LDO will behave as a constant current

source) set value. 100mA step, 0.1A-1.3A

0x00-0x0F: ILim = value * 0.1 (A)

Table 19. Battery Charge Status Register, CHG_Status (0x3E)[a]

Address

and Bit

R/W

Default

Value

Function and Description

0x3E [7:0]

Charge status

R/W

0x00

A WPC charge status packet will be sent based on the following:

0x0 = Reserved

0x1 = Charge status packet sent with parameter = 1 (1%)

0x2 = Charge status packet send with parameter = 2 (2%)

…

0x64 = Charge status packet send with parameter = 100 (100%)

0x65-0xFE = Reserved

0xFF = No battery charge device or not providing charge status packet

[a] After writing to this register, Send Charge Status bit of Command Register (0x4E) needs to be set for transmission to begin.

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