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P9222-R 数据表(PDF) 13 Page - Renesas Technology Corp

部件名 P9222-R
功能描述  Wireless Power Receiver for Low Power Applications
PDF  58 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

P9222-R 数据表(HTML) 13 Page - Renesas Technology Corp

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P9222-R/RN Datasheet
© 2019-2022 Renesas Electronics Corporation
13
May 5, 2022
Symbol
Description
Conditions
Minimum
Typical
Maximum
Unit
Analog-to-Digital Converter
N
Resolution
12
Bit
fSAMPLE
Sampling Rate
67.5
kSa/s
Channel
Number of Channels
8
#
VIN,FS
Full Scale Input
Voltage[e]
2.1
V
Thermal Shutdown
TSD
Thermal Shutdown[f]
Threshold rising
140
°C
Threshold falling
120
°C
Clock
fCLOCK_60
Clock Frequency
54
60
66
MHz
General Purpose Push-Pull Inputs/Outputs (GP0, GP1, /EN)
VIH_GP
Input High Level
1.4
V
VIL_GP
Input Low Level
0.5
V
ILKG_GP
Input Leakage Current
0V and 1.8V
-1
+1
µA
VOH_GP
Output Logic High
IOH = 4mA, 8mA total
1.44
V
VOL_GP
Output Logic Low
IOL = 8mA
0.36
V
SCL, SDA (OD0, OD1) and General Purpose Open Drain Inputs/Outputs (OD2, OD3, /INT)
VIH_OD
Input High Level[g]
1.4
V
VIL_OD
Input Low Level[g]
0.7
V
ILKG_OD
Input Leakage Current
V = 0V and 5V (1.8V for /INT)
-1
+1
µA
VOL_OD
Output Logic Low
IOL = 8mA
0.36
V
Ping Detection
VPDET_RC_IH
Input High Level
PDET_RC pin ≥ VPDET_RC_IH for
PDET_B pin to be pulled-low.
2.2
V
VPDET_RC_IL
Input Low Level
PDET_RC pin ≤ VPDET_RC_IL for
PDET_B pin to be pulled-high (external
pull-up required).
0.5
V
IPDET_RC_LKG
PDET_RC Leakage
VVRECT = 0V and VVRECT = 5.5V
-1
+1
μA
VPDETB_OL
Output Logic Low
IOL = 1mA
0.36
V
SCL, SDA (I2C Interface OD0, OD1)
fSCL
Clock Frequency
400
kHz
tHD_STA
Hold Time (Repeated)
for START Condition
0.6
µs
tHD_DAT
Data Hold Time
0
ns



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