AT89C51CC02CA-RATUM datasheet(61/156 Pages) ATMEL

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AT/T89C51CC02

4126J–CAN–05/06

Registers

Table 38. TCON Register

TCON (S:88h)

Timer/Counter Control Register

Reset Value = 0000 0000b

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

Number

Bit

Mnemonic

Description

7TF1

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

6TR1

Timer 1 Run Control bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer/Counter 1.

5TF0

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

4TR0

Timer 0 Run Control bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer/Counter 0.

3IE1

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (See IT1).

Set by hardware when external interrupt is detected on INT1# pin.

2IT1

Interrupt 1 Type Control bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (See IT0).

Set by hardware when external interrupt is detected on INT0# pin.

0IT0

Interrupt 0 Type Control bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

AT89C51CC02CA-RATUM 数据表(PDF) 61 Page - ATMEL Corporation

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