AT89C51CC02CA-RATUM datasheet(16/156 Pages) ATMEL

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AT/T89C51CC02

4126J–CAN–05/06

Clock

The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature,

called “X2”, provides the following advantages:

•

Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU

power.

•

Saves power consumption while keeping the same CPU power (oscillator power

saving).

•

Saves power consumption by dividing dynamic operating frequency by 2 in

operating and idle modes.

•

Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by the software.

An extra feature is available to start after Reset in the X2 Mode. This feature can be

enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section

’In-System Programming’.

Description

The X2 bit in the CKCON register (See Table 12) allows switching from 12 clock cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated

(STD mode).

Setting this bit activates the X2 feature (X2 Mode) for the CPU Clock only (See Figure

3).

The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 Mode only if the corre-

sponding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1

input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic

ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2

bit is validated on the XTAL1

÷ 2 rising edge to avoid glitches when switching from the

X2 to the STD mode. Figure 4 shows the mode switching waveforms.

AT89C51CC02CA-RATUM 数据表(PDF) 16 Page - ATMEL Corporation

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