AT89C51CC02CA-RATUM datasheet(21/156 Pages) ATMEL

21 / 156 page

AT/T89C51CC02

4126J–CAN–05/06

Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor

Note:

These values assume VDD starts from 0v to the nominal value. If the time between two

on/off sequences is too fast, the power-supply decoupling capacitors may not be fully

discharged, leading to a bad reset sequence.

During a Normal

Operation (Warm Reset)

Reset pin must be maintained for at least 2 machine cycles (24 oscillator clock periods)

to apply a reset sequence during normal operation. The number of clock periods is

mode independent (X2 or X1).

Watchdog Reset

A 1K resistor must be added in series with the capacitor to allow the use of watchdog

reset pulse output on the RST pin or when an external power-supply supervisor is used.

Figure 6 shows the reset circuitry when a capacitor is used.

Figure 6. Reset Circuitry for a Watchdog Configuration

Figure 7 shows the reset circuitry when an external reset circuit is used.

Figure 7. Reset Circuitry Example Using an External Reset Circuit

oscrst/vddrst

1ms

10ms

100ms

5ms

2.7µF

4.7µF

47µF

20ms

10µF

15µF

47µF

VDD

Rrst

Crst

RST pin

Internal reset

watchdog

To other on-board circuitry

Reset input circuitry

VDD

Rrst

RST pin

Internal reset

watchdog

To other on-board circuitry

Reset input circuitry

RST

External reset

circuit

AT89C51CC02CA-RATUM 数据表(PDF) 21 Page - ATMEL Corporation

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