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AT89C51CC02CA-RATUM 数据表(PDF) 36 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM 数据表(HTML) 36 Page - ATMEL Corporation |
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36 / 156 page  36 AT/T89C51CC02 4126J–CAN–05/06 Overview of FM0 Operations The CPU interfaces the Flash memory through the FCON register and AUXR1 register. These registers are used to: • Map the memory spaces in the adressable space • Launch the programming of the memory spaces • Get the status of the Flash memory (busy/not busy) Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EEE bit in EECON register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor- dance with Table 22. A MOVC instruction is then used for reading these spaces. Table 22. FM0 blocks Select bits Launching Programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 23 summarizes the memory spaces to program according to FMOD1:0 bits. Table 23. Programming Spaces Note: The sequence 5xh and Axh must be executing without instructions between them other- wise the programming is aborted. Interrupts that may occur during programming time must be disabled to avoid any spuri- ous exit of the programming mode. FMOD1 FMOD0 FM0 Adressable Space 0 0 User (0000h-3FFFh) 0 1 Extra Row(FF80h-FFFFh) 1 0 Hardware Security Byte (0000h) 11 Reserved Write to FCON Operation FPL3:0 FPS FMOD1 FMOD0 User 5 x 0 0 No action Ax 0 0 Write the column latches in user space Extra Row 5 x 0 1 No action Ax 0 1 Write the column latches in extra row space Hardware Security Byte 5 x 1 0 No action A x 1 0 Write the fuse bits space Reserved 5 x 1 1 No action A x 1 1 No action |
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