AT89C51CC02CA-RATUM datasheet(76/156 Pages) ATMEL

76 / 156 page

AT/T89C51CC02

4126J–CAN–05/06

Bit Shortening

If, on the other hand, the transmitter oscillator is faster than the receiver one, the next

falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N

is shortened in order to adjust the sample point for bit N+1 and the end of the bit time

Synchronization Jump Width

The limit to the amount of lengthening or shortening of the Phase Segments is set by the

Resynchronization Jump Width.

This segment may not be longer than Phase Segment 2.

Programming the Sample Point

Programming of the sample point allows "tuning" of the characteristics to suit the bus.

Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchroniza-

tion Jump Width can be programmed to its maximum. This maximum capacity to

shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances,

so that lower cost oscillators such as ceramic resonators may be used.

Late sampling allows more Time Quanta in the Propagation Time Segment which allows

a poorer bus topology and maximum bus length.

Arbitration

Figure 35. Bus Arbitration

The CAN protocol handles bus accesses according to the concept called “Carrier Sense

Multiple Access with Arbitration on Message Priority”.

During transmission, arbitration on the CAN bus can be lost to a competing device with

a higher priority CAN Identifier. This arbitration concept avoids collisions of messages

whose transmission was started by more than one node simultaneously and makes sure

the most important message is sent first without time loss.

The bus access conflict is resolved during the arbitration field mostly over the identifier

value. If a data frame and a remote frame with the same identifier are initiated at the

same time, the data frame prevails over the remote frame (c.f. RTR bit).

Errors

The CAN protocol signals any errors immediately as they occur. Three error detection

mechanisms are implemented at the message level and two at the bit level:

Error at Message Level

•

Cyclic Redundancy Check (CRC)

The CRC safeguards the information in the frame by adding redundant check bits at

the transmission end. At the receiver these bits are re-computed and tested against

the received bits. If they do not agree there has been a CRC error.

•

Frame Check

This mechanism verifies the structure of the transmitted frame by checking the bit

node A

TXCAN

node B

TXCAN

ID10 ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

SOF

RTR IDE

CAN bus

- - - - - - - - -

Arbitration lost

Node A loses the bus

Node B wins the bus

AT89C51CC02CA-RATUM 数据表(PDF) 76 Page - ATMEL Corporation

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