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AT89C51CC02CA-RATUM 数据表(PDF) 50 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM 数据表(HTML) 50 Page - ATMEL Corporation |
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50 / 156 page  50 AT/T89C51CC02 4126J–CAN–05/06 Hardware Security Byte Table 32. Hardware Security byte After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte. Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode. 76 54 32 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7X2B X2 bit Set this bit to start in standard mode Clear this bit to start in X2 Mode. 6BLJB Boot Loader Jump bit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5 - 3 - Reserved The value read from these bits are indeterminate. 2 - 0 LB2:0 Lock bits (see Table 22) |
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