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AT89C51CC02CA-RATUM 数据表(PDF) 46 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM 数据表(HTML) 46 Page - ATMEL Corporation |
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46 / 156 page  46 AT/T89C51CC02 4126J–CAN–05/06 Table 30. Read MOVC A, @DPTR Code Execution FCON Register ENBOOT DPTR FM1 FM0 XROW Hardware Byte FMOD1 FMOD0 FPS From FM0 00 X 0 0000h to 3FFFh OK 1 0000h to 3FFFh OK F800h to FFFFh Do not use this configuration 01 X X 0000 to 007Fh See (1) OK 10 X X X OK 11 X 0 000h to 3FFFh OK 1 0000h to 3FFFh OK F800h to FFFFh Do not use this configuration From FM1 (ENBOOT =1 00 0 1 0000h to 3FFF OK F800h to FFFFh OK 0X NA 1 1X OK 0X NA 01 X 1 0000h to 007h See (2) OK 0NA 10 X 1 X OK 0NA 11 X 1 000h to 3FFFh OK 0NA 1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh 2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh |
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