AT89C51CC02CA-RATUM datasheet(102/156 Pages) ATMEL

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102

AT/T89C51CC02

4126J–CAN–05/06

Table 67. CANBT3 Register

CANBT3 (S:B6h)

CAN bit Timing Registers 3

Note:

1. The CAN controller bit timing registers must be accessed only if the CAN controller is

disabled with the ENA bit of the CANGCON register set to 0.

See Figure 41.

No default value after reset.

PHS2 2

PHS2 1

PHS2 0

PHS1 2

PHS1 1

PHS1 0

SMP

Bit Number

Bit Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 - 4

PHS2 2:0

Phase Segment 2

This phase is used to compensate for phase edge errors. This

segment can be shortened by the re-synchronization jump width.

Phasse segment 2 is the maximum of Phase segment1 and the

Information Processing Time (= 2TQ).

3 - 1

PHS1 2:0

Phase Segment 1

This phase is used to compensate for phase edge errors. This

segment can be lengthened by the re-synchronization jump width.

0SMP

Sample Type

0 - once, at the sample point.

1 - three times, the threefold sampling of the bus is the sample

point and twice over a distance of a 1/2 period of the Tscl. The

result corresponds to the majority decision of the three values.

Tphs2 = Tscl x (PHS2[2..0] + 1)

Tphs1 = Tscl x (PHS1[2..0] + 1)

AT89C51CC02CA-RATUM 数据表(PDF) 102 Page - ATMEL Corporation

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