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数据搜索系统，热门电子元器件搜索 |
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AT89C51CC02CA-RATUM 数据表(PDF) 121 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM 数据表(HTML) 121 Page - ATMEL Corporation |
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121 / 156 page  121 AT/T89C51CC02 4126J–CAN–05/06 PCA Registers Table 95. CMOD Register CMOD (S:D9h) PCA Counter Mode Register Reset Value = 0XXX X000b 76 54 32 1 0 CIDL - - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7CIDL PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2-1 CPS1:0 EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 0ECF Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. |
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