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AT89C51CC02CA-RATUM 数据表(PDF) 135 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM 数据表(HTML) 135 Page - ATMEL Corporation |
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135 / 156 page  135 AT/T89C51CC02 4126J–CAN–05/06 Figure 58. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Reset Value = xxxx x000b bit addressable 76 54 32 1 0 - - - - ETIM EADC ECAN Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2ETIM TImer overrun Interrupt Enable bit Clear to disable the timer overrun interrupt. Set to enable the timer overrun interrupt. 1 EADC ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. 0ECAN CAN Interrupt Enable bit Clear to disable the CAN interrupt. Set to enable the CAN interrupt. |
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