ADIN1110CCPZ-R7 datasheet(38/107 Pages) AD

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Data Sheet

ADIN1110

MAC SPI

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Rev. B | 38 of 107

Table 33. Receive Latency for 16 MHz for All Supported Chunk Sizes

Chunk Size

(Bytes)

PHY Rx Latency (μs)

Time to Receive a Chunk

of Data on the Ethernet

Wire (μs) 1

Time to Start of Frame

Transfer over SPI (μs) 2

Total Rx Latency onto Wire

(μs)

Total Rx Latency to End of

First Chunk Transfer (μs) 3

6.4

57.6

6.4

47.4

56.4

6.4

19.2

30.6

35.6

6.4

12.8

22.2

25.2

1 Enough frame data to fill a chunk must be received before a transfer starts on the SPI. The time to receive the frame preamble is also included in this.

2 Assuming that the μC is not waiting for an interrupt and that it is providing back-to-back OPEN Alliance data transactions on the SPI. The frame transfers start in the middle

of the chunk on average.

3 Realistically, the μC cannot use the data until it receives the receive header at the end of the chunk.

Control Transactions

Table 34. Control Command Header

D31

D30

D29

D28

D27 to D24

D23 to D8

D7 to D1

HDRB

WNR

AID

MMS

ADDR [15:0]

LEN

Control transactions consist of one or more control commands.

These commands are used by the SPI host to read and write

registers within the MAC-PHY, and each one is composed of a

32-bit control command header followed by register data. See Table

34.

See the following definitions:

►

HDRB: received header bad. When set by the MAC-PHY, HDRB

indicates that a header was received with a parity error. The SPI

host must always clear this bit. The MAC-PHY ignores this value.

►

WNR: write not read. If 1, data is to be written to registers.

Otherwise, data is to be read.

►

AID: address increment disable. When clear, the address is

automatically post-incremented by one following each register

read or write.

►

MMS: memory map selector. This field selects the specific regis-

ter memory map to access. See Table 35.

►

ADDR: address of the first register within the selected memory

map to access.

►

LEN: length. Specifies the number of registers to read/write. This

field is interpreted as the number of registers − 1. Therefore, a

length of 0 reads or writes a single register.

►

P: parity. Parity bit calculated over the control command header.

Method used is odd parity.

Table 35. Register Memory Maps (MMS)

MMS

Memory Map Description

Standard control and status (SPI Address 0x00 to Address 0x20)

MAC (from SPI Address 0x30)

Control Write

The MAC-PHY ignores the final 32 bits of data from the SPI host at

the end of the control write command. The write command and data

is also echoed from the MAC-PHY back to the SPI so it can identify

which register write failed in the case of any bus errors.

Control write commands can write either a single or multiple regis-

ters. When multiple registers are written, the address is automati-

cally post incremented.

When a control write command is followed by another control

command, the new control header must immediately follow the last

word of the echoed register write data. The SPI host must deassert

CS following the last word of the echoed register write data when

the write command is the last command of the transaction.

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