ADIN1110CCPZ-R7 datasheet(48/107 Pages) AD

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Data Sheet

ADIN1110

REGISTERS

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Rev. B | 48 of 107

Table 41. Bit Descriptions for CAPABILITY (Continued)

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

[2:0]

MINCPS

Minimum Supported Chunk Payload Size (CPS). Indicates the minimum size chunk payload that can be

configured into the CPS field of the CONFIG0 register. The minimum supported chunk payload size is 2^N,

where N is the value of these bits. This field is only used with the OPEN Alliance SPI protocol.

0x3

110: minimum supported chunk payload size is 64 bytes.

101: minimum supported chunk payload size is 32 bytes.

100: minimum supported chunk payload size is 16 bytes.

011: minimum supported chunk payload size is 8 bytes.

Reset Control and Status Register

Address: 0x03, Reset: 0x00000000, Name: RESET

Table 42. Bit Descriptions for RESET

Bits

Bit Name

Description

Reset

Access

[31:1]

RESERVED

Reserved.

0x0

SWRESET

Software Reset. MAC-PHY Software Reset. The action of writing a 1 to this bit fully resets the MAC-PHY,

including the integrated PHY, to an initial state including, but not limited to, resetting all state machines and

registers to their default value. When this bit is set, the reset does not occur until CS is deasserted to allow for

the control command write to complete. CS must be held asserted for at least 100 ns for the reset to take effect.

This bit is self clearing.

0x0

Configuration Register 0

Address: 0x04, Reset: 0x00000006, Name: CONFIG0

Table 43. Bit Descriptions for CONFIG0

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

SYNC

Configuration Synchronization. The state of this bit is reflected in the Rx footer SYNC bit. This bit defaults

to 0 upon reset. When written to a 1 by the SPI host, writing 0 does not clear this bit. Immediately after any

reset, the SYNC bit clears to 0 and RESETC bit is set to 1, and the interrupt pin asserts.

0x0

R/W1S

0: the MAC-PHY has reset and is not configured.

1: the MAC-PHY is configured.

TXFCSVE

Transmit Frame Check Sequence Validation Enable. When set, the final 4 octets of all Ethernet frames

received are validated. CRC_APPEND must be 0 if this bit is set. That is, the MAC must not be configured

to append a CRC to each transmitted frame.

0x0

R/W

CSARFE

CS Align Receive Frame Enable. When set, all receive Ethernet frames data only start at the beginning of

the first receive chunk payload following CS assertion. The start word offset (SWO) is always 0. Receive

frames can begin within any receive chunk when this bit is clear. Only applies to the OPEN Alliance SPI

Protocol.

0x0

R/W

ZARFE

Zero Align Receive Frame Enable. When set, all receive Ethernet frames data are aligned to start at the

beginning of the receive chunk payload with a SWO of 0. Receive frames can begin anywhere within the

receive chunk payload when this bit is clear. Only applies to the OPEN Alliance SPI protocol.

0x0

R/W

[11:10]

TXCTHRESH

Transmit Credit Threshold. This field configures the number of transmit credits (TXC) of free buffer that

must be available for writing before IRQn is asserted. 00 ≥ 1 credit (default), 01 ≥ 4 credits, 10 ≥ 8 credits,

and 11 ≥ 16 credits. Only applies to the OPEN Alliance SPI Protocol.

0x0

R/W

00: ≥1 credit.

01: ≥4 credit.

10: ≥8 credit.

11: ≥16 credit.

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