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ADIN1110CCPZ-R7 数据表(PDF) 83 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 83 Page - Analog Devices |
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83 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 83 of 107 Table 150. Bit Descriptions for AN_STATUS (Continued) Bits Bit Name Description Reset Access 4 AN_REMOTE_FAULT Autonegotiation Remote Fault. Remote fault set in base page received from link partner. 0x0 R LH 3 AN_ABLE Autonegotiation Ability. When this bit is read as 1, it indicates that the PHY is able to perform autonegotiation. 0x1 R 2 AN_LINK_STATUS Link Status. When read as 1, this bit indicates that a valid link is established. If this bit reads 0, it means that the link has failed since the last time it was read. 0x0 R LL [1:0] RESERVED Reserved. 0x0 R BASE-T1 Autonegotiation Advertisement Register, Bits[15:0] Device Address: 0x07; Register Address: 0x0202, Reset: 0x0001, Name: AN_ADV_ABILITY_L This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits[15:0] specified in Clause 45.2.7.21 of Standard 802.3. Table 151. Bit Descriptions for AN_ADV_ABILITY_L Bits Bit Name Description Reset Access 15 AN_ADV_NEXT_PAGE_REQ Next Page Request. This bit indicates to the link partner that the PHY wants to send a next page. See IEEE Standard 802.3 subclause 98.2.1.2.9. 0x0 R/W 14 AN_ADV_ACK Acknowledge (ACK). This bit indicates that the device has received the link codeword of its link partner. See IEEE Standard 802.3 Subclause 98.2.1.2.8. 0x0 R 13 AN_ADV_REMOTE_FAULT Remote Fault. See IEEE Standard 802.3 Subclause 98.2.1.2.7. 0x0 R/W 12 AN_ADV_FORCE_MS Force Master/slave Configuration. This bit allows the PHY to force its master/slave configuration. When this bit is set as 0, the master/slave configuration is a preferred mode. (The configuration in AN_ADV_MST is a preferred configuration.) If this bit is set to 1, the master/slave configuration is a forced mode. (The configuration in AN_ADV_MST is a forced configuration.) See IEEE Standard 802.3 Subclause 98.2.1.2.5 for more details. 0x0 R/W [11:10] AN_ADV_PAUSE Pause Ability. This bit field advertises support for asymmetric and symmetric pause functions on full duplex links. See IEEE Standard 802.3 Subclause 98.2.1.2.6 for more details. 0x0 R/W [9:5] RESERVED Reserved. 0x0 R [4:0] AN_ADV_SELECTOR Selector. The value of this field is fixed at 5'b00001, which is the IEEE 802.3 selector value. See IEEE Standard 802.3 Subclause 98.2.1.2.1. 0x1 R BASE-T1 Autonegotiation Advertisement Register, Bits[31:16] Device Address: 0x07; Register Address: 0x0203, Reset: 0x4000, Name: AN_ADV_ABILITY_M This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits[31:16], specified in Clause 45.2.7.21 of Standard 802.3. Table 152. Bit Descriptions for AN_ADV_ABILITY_M Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R 14 AN_ADV_B10L 10BASE-T1L Ability. This bit indicates that the device is compatible with 10BASE-T1L. 0x1 R/W [13:5] RESERVED Reserved. 0x0 R 4 AN_ADV_MST Master/slave Configuration. This bit advertises the master/slave configuration, as follows: 0: slave, 1: master. See also the AN_ADV_FORCE_MS bit, which determines whether this bit expresses a preference or a forced value. See IEEE Standard 802.3 Subclause 98.2.1.2.3 (master/slave configuration is Bit 4 of the transmitted nonce field). Pin Dependent R/W [3:0] RESERVED Reserved. 0x0 R |
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