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ADIN1110CCPZ-R7 数据表(PDF) 50 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 50 Page - Analog Devices |
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50 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 50 of 107 Table 44. Bit Descriptions for CONFIG2 (Continued) Bits Bit Name Description Reset Access 0: select the SFD from the PHY. This option provides the least jitter as the SFD is detected in the same 120 MHz clock domain as is used in 1588 timer logic. 1: select the SFD from the MAC. The SFD from the MAC is from the 25 MHz clock domain and results in additional jitter on the SFD detection. 6 STATS_CLR_ON_RD Statistics Clear on Reading. This field determines if the following registers/counters are cleared on reading: P1_RX_FRM_CNT, P1_RX_BCAST_CNT, P1_RX_MCAST_CNT, P1_RX_UCAST_CNT, P1_RX_CRC_ERR_CNT,P1_RX_ALGN_ERR_CNT, P1_RX_LS_ERR_CNT, P1_RX_PHY_ERR_CNT, P1_TX_FRM_CNT, P1_TX_BCAST_CNT, P1_TX_MCAST_CNT, P1_TX_UCAST_CNT, P1_RX_DROP_FULL_CNT, P1_RX_DROP_FILT_CNT, P1_RX_IFG_ERR_CNT, and CECC_ERRn 0x0 R/W 0: statistic counter is not cleared on reading. When the maximum value is reached, the counters roll over to 0x0. 1: clear statistics counters on reading. If a counter reaches its maximum value, the counter holds at its maximum until read. When using the generic SPI protocol, the status counters must be burst read in one SPI transaction to ensure all counters are cleared properly in sequence. If a single SPI register/counter is read, it clears and the next counter (address location) also clears when using the generic SPI protocol. 5 CRC_APPEND Enable CRC Append. Enable CRC append in the MAC Tx path. Enables (1) or disables (0) CRC appendage by the MAC. If this field is set to 0, the MAC assumes that the host is providing a frame with a valid CRC header at the end. It is recommended that the host always appends a CRC32 with the frame as this provides errors detection over the SPI for transmitted frames. The CRC32 is checked as the frame is transmitted. If an error is detected, TXFCSE asserts. Similarly, on receive, the CRC32 is forwarded with the frame to the host where the host must verify it is correct. 0x0 R/W 4 P1_RCV_IFG_ERR_FRM Admit Frames with IFG Errors on Port 1 (P1). If enabled, the MAC admits frames with IFG errors on Port 1. Enables reception of frames that violate the minimum IFG requirement on Port 1. 0x0 R/W 3 RESERVED Reserved. 0x0 R/W 2 P1_FWD_UNK2HOST Forward Frames Not Matching Any MAC Address to the Host. Determines the default rule for forwarding unknown frames. Frames with an unknown destination address are placed in the low priority FIFO. 0x0 R/W [1:0] MSPEED SPI to MDIO Bridge MDC Clock Speed. 0x0 R/W 00: 2.5 MHz. 01: 4.166 MHz. Status Register 0 Address: 0x08, Reset: 0x00000040, Name: STATUS0 Table 45. Bit Descriptions for STATUS0 Bits Bit Name Description Reset Access [31:13] RESERVED Reserved. 0x0 R 12 CDPE Control Data Protection Error. When control data read/write protection is enabled, this bit indicates that the MAC-PHY detected an error in protected control write data received from the host. When not implemented, this bit must be reserved with a read-only value of 0. This field is only used with the OPEN Alliance SPI protocol. 0x0 R/W1C 11 TXFCSE Transmit Frame Check Sequence Error. This bit indicates that a frame was received over SPI from the host with an invalid FCS appended. The frame is still forwarded from the device because the FCS is checked as the frame is being transmitted. 0x0 R/W1C 10 TTSCAC Transmit Time Stamp Capture Available C. 0x0 R/W1C 9 TTSCAB Transmit Time Stamp Capture Available B. 0x0 R/W1C 8 TTSCAA Transmit Time Stamp Capture Available A. 0x0 R/W1C |
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