ADIN1110CCPZ-R7 datasheet(16/107 Pages) AD

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Data Sheet

ADIN1110

THEORY OF OPERATION

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Rev. B | 16 of 107

Typical Use

The LED_0 and LED_1 pins can be used to connect external

LEDs to indicate the ADIN1110 link status and transmit or receive

activity. The activity assigned to each LED is configurable through

LED_CNTRL (see the LED Control Register section).

The LED pins are suitable for ultra low power LEDs. The maximum

output current for the LED_0 and LED_1 pins is 8 mA with a VDDIO

= 3.3 V. For higher LED power requirements, the use of an external

transistor is recommended.

The LED_x pins can also be connected to a host microcontroller

general-purpose input/output (GPIO) (configured as a pulse-width

modulated input or hardware interrupt). This configuration can be

useful in applications where the user interface needs to be fully

handled by an external host controller (for example, an external

LED module or display). Note that in this context, it is recommend-

ed to place a low value resistance in series between the ADIN1110

LED_x pins and the controller to avoid any potential transient surge

current.

LED Pin Multiplexing

An internal multiplexer needs to be configured to enable the LED_1

signal on the LED_1 pin. LED_1 is disabled by default and can

be enabled using the DIGIO_LED1_PINMUX bits (see the Pin Mux

Configuration 1 Register section).

The LED_0 pin does not need multiplexing.

LED Polarity

The LED_0 and LED_1 pins can be configured to support various

LED circuit polarities through the LED polarity mode feature (see

the LED Polarity Register section). Three polarity modes are availa-

ble for each LED, as follows:

►

Autosense (default)

►

Active high

►

Active low

In autosense mode, the ADIN1110 automatically senses the pin at

power-up or reset to select the appropriate polarity configuration. In

active high mode, the ADIN1110 is configured to drive the LED from

the anode side. In active low mode, the ADIN1110 is configured to

drive the LED from the cathode side.

Example circuits are described in the LED Circuit Examples sec-

tion.

LED Mode

LED_0 and LED_1 activity behavior can be configured using the

two LED modes, as follows:

►

LED Mode 1: blink duty cycle defined using the

LED0_BLINK_TIME_CNTRL register (see the LED_0 On/Off

Blink Time Register section) and LED1_BLINK_TIME_CNTRL

respectively

►

LED Mode 2: blink duty cycle automatically defined by the

ADIN1110 based on activity level (%)

LINK STATUS PIN

The LINK_ST pin is asserted high when the link status bit

(AN_LINK_STATUS) is asserted and indicates that the link between

the ADIN1110 and its link partner is active.

By default, the LINK_ST signal is active high and can be con-

figured to be either active high or active low using the DIG-

IO_LINK_ST_POLARITY bit (see the Pin Mux Configuration 1

POWER-DOWN MODES

The ADIN1110 supports two power-down modes, as follows:

►

Hardware power-down

►

Software power-down

The lowest power mode is hardware power-down mode in which

the device is turned off and the registers are not accessible.

Hardware Power-Down Mode

Hardware power-down mode can be used when no operation is

required on the ADIN1110 and the power consumption needs to

be minimized. The ADIN1110 enters hardware power-down mode

when the RESET pin is asserted and held low. In this mode, all

analog and digital circuits are disabled, the clocks are gated off, all

the I/O pins are held in tristate mode, and the only power is the

leakage power of the circuits. The management registers are not

accessible in this mode.

Software Power-Down Mode

Software power-down mode can be used to configure the

ADIN1110 registers before bringing a link up. The ADIN1110 can

be configured to enter software power-down mode after reset using

the SWPD_EN pin. The ADIN1110 can also be instructed to enter

software power-down mode by setting the software power-down bit

(CRSM_SFT_PD).

The software power-down status bit (CRSM_SFT_PD_RDY) indi-

cates that the device is in the software power-down state. In

software powerdown mode, the analog and digital circuits are in

a low power state, and the PLL is active and can provide output

clocks if configured to do so. Any signal or energy on the MDI pins

is ignored and no link is brought up. The management interface

registers are accessible, and the device can be configured using

software. The ADIN1110 exits software power-down mode when the

CRSM_SFT_PD bit is cleared. At this point, the MAC-PHY starts

autonegotiation and attempts to bring up a link after autonegotiation

completes.

ADIN1110CCPZ-R7 数据表(PDF) 16 Page - Analog Devices

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