ADIN1110CCPZ-R7 datasheet(49/107 Pages) AD

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Data Sheet

ADIN1110

REGISTERS

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Rev. B | 49 of 107

Table 43. Bit Descriptions for CONFIG0 (Continued)

Bits

Bit Name

Description

Reset

Access

TXCTE

Transmit Cut Through Enable. This bit enables the cut through mode of frame transfer through the

MAC-PHY device from the SPI host to the network. When cut through on Tx is enabled, the host must

ensure that data is provided to the device at a rate of >10 Mbps to ensure frame transmission does not

under run.

0x0

R/W

RXCTE

Receive Cut Through Enable. This bit enables the cut through mode of frame transfer through the

MAC-PHY device from the network to the SPI host. Cut through must be enabled on device configuration

before receiving frames is enabled. That is, enable cut through before setting P1_FWD_UNK2HOST or

writing to the ADDR_FILT_x registers. RXCTE must be 0 when using the generic SPI protocol.

0x0

R/W

FTSE

Frame Time Stamp Enable. This bit enables IEEE 1588 receive and transmit frame time stamps.

0x0

R/W

0: frame receive/transmit time stamps are disabled.

1: frame receive/transmit time stamps are enabled.

FTSS

Receive Frame Time Stamp Select. When supported by this MAC-PHY device and enabled by FTSE = 1,

this bit configures the size and format of the time stamps appended to received frames and capture on

request of transmit frames.

0x0

R/W

0: 32-bit time stamps.

1: 64-bit time stamps.

PROTE

Enable Control Data Read Write Protection. When set and using the OPEN Alliance SPI protocol, all

control data written to and read from the MAC-PHY is transferred with its complement for detection of bit

errors. When set and using the generic SPI protocol, a CRC8 must be provided on SDI, and read data on

SDO provides a CRC8. Note this bit cannot be written. Its value is set via sensing a pin on power-up.

0x0

SEQE

Enable TX Data Chunk Sequence and Retry. When supported by this MAC-PHY device, this bit enables

MAC-PHY monitoring of the SEQ bit transmitted in the Tx data chunk header by the SPI host and Tx data

chunk retries. 0: support for Tx data chunk sequence and retry is disabled. The MAC-PHY ignores the Tx

header SEQ bit. 1: support for Tx data chunk sequence and retry is enabled. The MAC-PHY monitors the

SEQ bit in the Tx header and allows rewriting of the Tx data chunks when the SEQ bit does not change.

Not supported. Only applies to the OPEN Alliance SPI protocol.

0x0

R/W

RESERVED

Reserved.

0x0

[2:0]

CPS

Chunk Payload Selector (N). Chunk Payload Size is 2^N. N = 3 minimum and 6 maximum. Default is 64

bytes. This field must be set on device configuration before frame transmission from the host starts and

before enabling receiving frames into the Rx FIFOs. This field cannot be modified while transmitting a

frame from the host or while sending a received frame to the host. Once the configuration synchronization

(SYNC) bit is set, the chunk payload size does not change without a reset of the MAC-PHY. The minimum

supported chunk payload size for this MAC-PHY device is indicated in the CPSMIN field of the capability

0x6

R/W

011: chunk size is 8 bytes.

100: chunk size is 16 bytes.

101: chunk size is 32 bytes.

110: chunk size is 64 bytes.

Configuration Register 2

Address: 0x06, Reset: 0x00000800, Name: CONFIG2

Vendor specific.

Table 44. Bit Descriptions for CONFIG2

Bits

Bit Name

Description

Reset

Access

[31:9]

RESERVED

Reserved.

0x4

TX_RDY_ON_EMPTY

Assert TX_RDY When the Tx FIFO is Empty. By default, TX_RDY asserts when a frame

transmits. If this bit is set, TX_RDY asserts when the Tx FIFO is empty. This field is only used

with the generic SPI protocol.

0x0

R/W

SFD_DETECT_SRC

Determines If the SFD is Detected in the PHY or MAC.

0x0

R/W

ADIN1110CCPZ-R7 数据表(PDF) 49 Page - Analog Devices

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