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ADIN1110CCPZ-R7 数据表(PDF) 80 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 80 Page - Analog Devices |
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80 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 80 of 107 Table 138. Bit Descriptions for B10L_PMA_LINK_STAT (Continued) Bits Bit Name Description Reset Access 9 B10L_REM_RCVR_STAT_OK_LL 10BASE-T1L Remote Receiver Status OK Latch Low. Latched low version of B10L_REM_RCVR_STAT_OK. 0x0 R LL 8 B10L_REM_RCVR_STAT_OK 10BASE-T1L Remote Receiver Status OK. When read as 1, this bit indicates that the remote receiver status is OK. 0x0 R 7 B10L_LOC_RCVR_STAT_OK_LL 10BASE-T1L Local Receiver Status OK Latch Low. Latched low version of B10L_LOC_RCVR_STAT_OK. 0x0 R LL 6 B10L_LOC_RCVR_STAT_OK 10BASE-T1L Local Receiver Status OK. When read as 1, this bit indicates that the local receiver status is OK. 0x0 R 5 B10L_DSCR_STAT_OK_LL BASE-T1L Descrambler Status OK Latch Low. When read as 1, this bit indicates that the descrambler status is OK. 0x0 R LL 4 B10L_DSCR_STAT_OK 10BASE-T1L Descrambler Status OK. When read as 1, this bit indicates that the descrambler status is OK. 0x0 R [3:2] RESERVED Reserved. 0x0 R 1 B10L_LINK_STAT_OK_LL Link Status OK Latch Low. When read as 1, this bit indicates that the link status is OK. 0x0 R LL 0 B10L_LINK_STAT_OK Link Status OK. When read as 1, this bit indicates that the link status is OK. 0x0 R MSE Value Register Device Address: 0x01; Register Address: 0x830B, Reset: 0x0000, Name: MSE_VAL Table 139. Bit Descriptions for MSE_VAL Bits Bit Name Description Reset Access [15:0] MSE_VAL MSE Value. Note that the LSB weight is 2−18. When computing a signal-to-noise ratio (SNR) value, the mean 10BASE-T1L idle symbol power is 0.64422. 0x0 R PCS Control 1 Register Device Address: 0x03; Register Address: 0x0000, Reset: 0x0000, Name: PCS_CNTRL1 This address corresponds to the PCS Control Register 1 specified in Clause 45.2.3.1 of Standard 802.3. Table 140. Bit Descriptions for PCS_CNTRL1 Bits Bit Name Description Reset Access 15 PCS_SFT_RST PCS Software Reset. Mirrors PMA_SFT_RST. 0x0 R/W SC 14 LB_PCS_EN PCS Loopback Enable. When this bit is set to 1, the PCS accepts data on the transmit path and returns it on the receive path. When this bit is set to 0, the PCS works in normal mode. 0x0 R/W [13:12] RESERVED Reserved. 0x0 R 11 PCS_SFT_PD PCS Software Power-Down. Mirrors PMA_SFT_PD 0x0 R/W [10:0] RESERVED Reserved. 0x0 R PCS Status 1 Register Device Address: 0x03; Register Address: 0x0001, Reset: 0x0002, Name: PCS_STAT1 Table 141. Bit Descriptions for PCS_STAT1 Bits Bit Name Description Reset Access [15:2] RESERVED Reserved. 0x0 R 1 PCS_SFT_PD_ABLE PCS Software Power-Down Able. Indicates that the PCS supports software power-down. 0x1 R 0 RESERVED Reserved. 0x0 R |
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