ADIN1110CCPZ-R7 datasheet(40/107 Pages) AD

40 / 107 page

Data Sheet

ADIN1110

MAC SPI

analog.com

Rev. B | 40 of 107

►

Transmit Buffer Overflow. Occurs when attempting to write trans-

mit frame data to the MAC-PHY when there is no transmit buffer

space available as indicated by the transmit credit field (TXC) of

the previous data footer. In this condition, the MAC-PHY ignores

the transmit data chunk and sets the host transmit FIFO overflow

bit, and the frame data already in the buffer is dropped.

►

Transmit Buffer Under Run. This error can only occur in cut

through mode. The SPI host must always send frame data to

the MAC-PHY faster than the network to avoid this error. When

this error occurs, the host transmit FIFO under run error bit is

set, and the MAC-PHY terminates the frame being transmitted

in a way that invalidates the frame. Additionally, the MAC-PHY

ignores any additional frame data received from the SPI host

until it receives an end of frame indication (EV = 1).

►

Loss of Framing Error. This error occurs when the CS signal is

deasserted before the expected end of the data chunk or control

command. The MAC-PHY and the loss of frame error is set, any

transmit frame in progress is dropped, and any receive frame in

progress of being sent to the SPI host is terminated.

►

Receive Buffer Overflow. This error occurs when the SPI host

does not read frame data from the MAC-PHY fast enough. This

error can occur both in store and forward and cut through modes.

When this error occurs, the MAC-PHY terminates the frame

being received from the PHY. In store and forward mode, no

portion of the frame is transferred to the SPI host. In cut through

mode, the MAC-PHY terminates the frame (EV = 1) with frame

drop set (FD = 1).

►

Control Data Protection Error. The control data protection error

(CDPE) and the loss of frame error (LOFE) bits assert when

protection is enabled on the OPEN Alliance SPI and there is an

error on write data received from the host. The write does not

complete in this case.

If possible, the software executes the write again. If software

does not know which configuration register was written, the de-

vice might not be configured properly. In this case, the MAC must

be reset by writing the RST_MAC_ONLY keys to the software

reset register.

SPI Access to the PHY Registers

The ADIN1110 provides indirect access using the SPI to access the

PHY management registers. The 8 registers MDIOACCn in the SPI

Each MDIOACCn register corresponds to an MDIO transaction.

The MDC default speed is 2.5 MHz. Either 2.5 MHz or 4.166

MHz MDC frequency can be selected via the MSPEED bits in the

CONFIG2 register.

The MDIO master polls in round robin mode the TRDONE bits of

the eight MDIOACCn registers. When the MDIO master detects that

one of the TRDONE fields is 0, an MDIO transaction is started

by the MDIO master. When the MDIO transaction completes, the

TRDONE bits are set to 1, and the master proceeds to check the

TRDONE bits of the next MDIOACCn register.

Note that MDIO_DEVAD is always written with the device ID of the

and MDIO_ST is written to 0x0 for Clause 45 access (this applies to

all of the following examples).

Example write to PHY Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = the address of Regis-

ter XYZ, MDIO_DEVAD = the device ID of Register XYZ,

MDIO_PRTAD = 0x1, MDIO_OP = 0x0(ADDR), MDIO_ST =

0x0, and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DATA = the value to be written to

3. Optionally, poll MDIOACC0.TRDONE = 0x1 to determine that

the write address operation has completed.

4. Poll MDIOACC1.TRDONE = 0x1 to determine that the write

data operation has completed.

Example read of PHY Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = the address of Register

XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_OP = 0x3(RD) and TRDONE =

0x0.

3. Poll MDIOACC1. TRDONE= 0x1 to determine that the write da-

ta operation has completed. MDIOACC1. MDIO_DATA reflects

the content of MDIO Register XYZ.

Example write operation followed by a read to verify the write

operation:

1. Write MDIOACC0 with MDIO_DATA = the address of register

ABC and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DATA = the value to be written to

3. Write MDIOACC2 MDIO_OP = 0x3(RD) and TRDONE = 0x0.

4. Poll MDIOACC2.TRDONE = 0x1 to verify that all operations are

completed. MDIO_DATA reflects the content of register ABC.

Example of four consecutive writes. It is possible to write a com-

mand to all 8 register before checking any.

1. Write MDIOACC0 with MDIO_DATA = the address of register

ABC and TRDONE = 0x0.

2. Write MDIOACC1 with the write data for register ABC,

MDIO_OP = 0x1, and TRDONE = 0x0.

3. Write MDIOACC2 with MDIO_DATA = the address of register

DEF and TRDONE = 0x0.

4. Write MDIOACC3 with the write data for register DEF,

MDIO_OP = 0x1, and TRDONE = 0x0.

5. Write MDIOACC4 with MDIO_DATA = the address of register

GHJ and TRDONE = 0x0.

6. Write MDIOACC5 with the write data for register GHJ,

MDIO_OP = 0x1, and TRDONE = 0x0.

ADIN1110CCPZ-R7 数据表(PDF) 40 Page - Analog Devices

ADIN1110CCPZ-R7 数据表(HTML) 40 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADIN1110CCPZ-R7 数据表(PDF) 40 Page - Analog Devices

ADIN1110CCPZ-R7 数据表(HTML) 40 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载