ADIN1110CCPZ-R7 datasheet(14/107 Pages) AD

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Data Sheet

ADIN1110

THEORY OF OPERATION

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Rev. B | 14 of 107

RESET OPERATION

The ADIN1110 supports the following chip resets:

►

Power-on reset

►

Hardware reset

►

Software reset

►

MAC subsystem reset

►

PHY subsystem reset

All of these resets put the ADIN1110, including the PHY core and

MAC, into a known state. Whenever the MAC is reset, the SDO pin

is pulled down and the TS_TIMER pin is driven to a low state.

Power-On Reset

The ADIN1110 includes power monitoring circuitry to monitor all of

the supplies. During power-up, the ADIN1110 is held in hardware

reset until each of the supplies has crossed its minimum rising

threshold value and the power is considered good.

The POR module includes brownout protection by monitoring the

supplies to detect if one or more of the supplies falls below a

minimum falling threshold value. If brownout detection occurs, the

device is held in hardware reset until the power is good.

Hardware Reset

A hardware reset is initiated by the power-on reset circuitry or

by asserting the RESET pin low. Bring the RESET pin low for a

minimum of 10 µs. Deglitch circuitry is included on this pin to reject

pulses shorter than 0.3 μs.

When the RESET pin is deasserted, all the input/output (I/O) pins

are held in tristate mode, the hardware configuration pins are latch-

ed, and the I/O pins are configured for their functional mode. When

all the external and internal supplies are valid and stable, the crystal

oscillator circuit is enabled. After the crystal starts up and stabilizes,

the phase-locked loop PLL is enabled. After approximately 50 ms

(maximum) from the deassertion of the RESET pin, all the internal

clocks are valid, internal logic is released from reset, and all the

management interface registers are accessible so that the device

can be programmed.

Software Reset

A full chip software reset can be initiated by writing 1 to the

SWRESET field of the RESET register.

If a transmission is taking place when the SPI software reset is initi-

ated, the frame transmission stops abruptly and a runt or a frame

with a bad cyclic redundancy check (CRC) may be transmitted.

Once the MAC-PHY is reset, the ADIN1110 is ready to bring up

links.

When this software reset is initiated, a full initialization of the chip,

almost equivalent to a hardware reset, is done. The I/O pins are

held in tristate mode, the hardware configuration pins are latched,

and the I/O pins are configured for their functional mode. The crys-

tal oscillator circuit is enabled, and after the crystal starts up and

stabilizes, the PLL is enabled. Approximately 10 ms (maximum)

after writing the SOFT_RST keys, the internal logic is released from

reset and all the management interface registers are accessible.

MAC Subsystem Reset

A MAC only software reset is initiated by writing the required pair of

keys to the SOFT_RST register.

The reset is applied for about 1.2 µs. The MAC subsystem reset

interrupts any transmit/receive packet exchange between the MAC

and the PHY, but does not drop any existing link nor prevents

a link from establishing. The PHY management registers are not

initialized.

The PHY needs to be out of software power-down to trigger a MAC

only software reset.

PHY Subsystem Reset

The PHY subsystem is the part of the ADIN1110 that incorporates

the 10BASE-T1L PHY transceiver analog and digital circuits. A

PHY subsystem reset is initiated by setting the PHY subsystem

reset register bit (CRSM_PHY_SUBSYS_RST). When this bit is

set, the PHY subsystem is reset. The reset is applied for about

1.2 µs and then this bit self clears. All of the PHY digital circuitry

is reset and any existing link drops. The management registers

are not initialized by this reset, and access to all the management

registers is available during the PHY subsystem reset. This is a

short reset and can be used to put the device into a known state

while retaining any software initialization of the device.

LED FUNCTIONS

LED_0 and LED_1 can be configured to display various activities

of the ADIN1110 using the LED function feature. The LED function

is configurable using the LED0_FUNCTION and LED1_FUNCTION

bits (see the LED Control Register section).

The 7, 8, 9, and 10 (decimal) bit settings for LEDx_FUNCTION are

not available in LED Mode 2.

Table 10. LED_x Pins Configuration Summary

Parameter

LED_0

LED_1

Pin Number

Internal Pull-Up or Pull-

Down Resistor

Pull-up

Pull-down

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