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ADIN1110CCPZ-R7 数据表(PDF) 52 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 52 Page - Analog Devices |
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52 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 52 of 107 Table 46. Bit Descriptions for STATUS1 (Continued) Bits Bit Name Description Reset Access 4 P1_RX_RDY Port 1 Rx FIFO Contains Data. In store and forward mode, this field indicates that there are 1 or more frames in Port 1 Rx FIFO. In cut through mode, this field indicates that the receive threshold (RX_THRESH) is reached or the EOF byte of a frame is received. If there are frames in both the Rx high and low priority FIFOs, the frame from the high priority FIFO is read first by default. This field is only used with the generic SPI protocol. 0x0 R 3 TX_RDY Tx Ready. If TX_RDY_ON_EMPTY is 0, TX_RDY asserts when frame transmission completes. If TX_RDY_ON_EMPTY is 1, TX_RDY asserts when the Tx FIFO is empty and frame transmission completes. This bit is cleared by writing 1 to this field. This field is only used with the generic SPI protocol. 0x0 R/W1C 2 RESERVED Reserved. 0x0 R 1 LINK_CHANGE Link Status Changed. Indicates that the link status has changed on Port 1. 0x0 R/W1C 0 P1_LINK_STATUS Port 1 Link Status. This bit does not generate an interrupt event. 0x0 R 0: link down. 1: link pp. Buffer Status Register Address: 0x0B, Reset: 0x00007700, Name: BUFSTS Table 47. Bit Descriptions for BUFSTS Bits Bit Name Description Reset Access [31:16] RESERVED Reserved. 0x0 R [15:8] TXC Transmit Credits Available. Number of chunk buffers of transmit data currently available for the SPI host to write. Reading this field allows the SPI host to queue up the number of transmit chunks available into a single DMA, if desired. The value in this field is saturated to 31 and sent in the 5-bit TXC field of every RX data footer. The default (maximum) number of transmit buffer credits available is implementation specific. This field is only used with the OPEN Alliance SPI protocol 0x77 R [7:0] RCA Receive Chunks Available. Number of chunks of receive data currently available for the SPI host to read. Reading this field allows the SPI host to queue up the number of receive chunks available into a single DMA, if desired. This field is only used with the OPEN Alliance SPI protocol. 0x0 R Interrupt Mask Register 0 Address: 0x0C, Reset: 0x00001FBF, Name: IMASK0 Table 48. Bit Descriptions for IMASK0 Bits Bit Name Description Reset Access [31:13] RESERVED Reserved. 0x0 R 12 CDPEM Control Data Protection Error Mask. Setting this bit to 1 prevents the control data protection error status bit in STATUS0 from asserting the footer EXST bit. This field is only used with the OPEN Alliance SPI protocol. 0x1 R/W 11 TXFCSEM Transmit Frame Check Sequence Error Mask. Setting this bit to 1 prevents the transmit frame check sequence error status bit in STATUS0 from asserting the interrupt pin. 0x1 R/W 10 TTSCACM Transmit Time Stamp Capture Available C Mask. Setting this bit to 1 prevents the Transmit Time Stamp Capture Available C status bit in STATUS0 from asserting the footer EXST bit. 0x1 R/W 9 TTSCABM Transmit Time Stamp Capture Available B Mask. Setting this bit to 1 prevents the Transmit Time Stamp Capture Available B status bit in STATUS0 from asserting the footer EXST bit. 0x1 R/W 8 TTSCAAM Transmit Time Stamp Capture Available A Mask. Setting this bit to 1 prevents the Transmit Time Stamp Capture Available A status bit in STATUS0 from asserting the footer EXST bit. 0x1 R/W 7 PHYINTM Physical Layer Interrupt Mask. Setting this bit to 1 prevents the physical layer interrupt (PHYINT) status bit in STATUS0 from asserting the footer EXST bit. 0x1 R/W 6 RESETCM RESET Complete Mask. This bit is reserved as a mask for the reset complete (RESETC) status bit. This bit is read only and always 0 because the RESETC status bit is a non maskable interrupt that causes IRQn to always assert when RESETC is set. 0x0 R |
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